74AHC164PW原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

74AHC164; 74AHCT164

8-bit serial-in/parallel-out shift register

Rev. 03 — 24 April 2008

Product data sheet

1. General description

The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with

JEDEC standard No. 7A.

The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA

or DSB); either input can be used as an active HIGH enable for data entry through the

other input. Both inputs must be connected together or an unused input must be tied

HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)

and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)

that existed one set-up time prior to the rising clock edge.

A LOW-level on the master reset (MR) input overrides all other inputs and clears the

register asynchronously, forcing all outputs LOW.

2. Features

I Balanced propagation delays

I All inputs have Schmitt-trigger actions

I Inputs accept voltages higher than V_CC

I Input levels:

N For 74AHC164: CMOS level

N For 74AHCT164: TTL level

I ESD protection:

N HBM EIA/JESD22-A114E exceeds 2000 V

N MM EIA/JESD22-A115-A exceeds 200 V

N CDM EIA/JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AHC164

74AHC164D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

SOT402-1

74AHC164PW

74AHC164BQ

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1

thin quad ﬂat package; no leads; 14 terminals; body

2.5 × 3 × 0.85 mm

74AHCT164

74AHCT164D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

SOT402-1

74AHCT164PW −40 °C to +125 °C

74AHCT164BQ −40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1

thin quad ﬂat package; no leads; 14 terminals; body

2.5 × 3 × 0.85 mm

4. Functional diagram

1

DSA

2

8

9

DSB

8-BIT SERIAL−IN/PARALLEL−OUT

CP

SHIFT REGISTER

MR

3

4

5

6

10 11 12 13

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

001aac425

Fig 1. Functional diagram

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

2 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

SRG8

8

C1/

9

R

1

3

&

1D

2

4

5

3

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

DSA

1

6

4

2

DSB

5

10

11

12

13

6

10

11

CP

8

9

12

MR

13

001aac424

001aac423

Fig 2. Logic symbol

Fig 3. IEC logic symbol

DSA

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

CP

DSB

FF1

FF2

FF3

FF4

FF5

FF6

FF7

FF8

R

D

R

D

R

D

R

D

R

D

R

D

R

D

R

D

CP

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

001aac616

Fig 4. Logic diagram

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

3 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

5. Pinning information

5.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

14

13

12

11

10

9

DSA

DSB

Q0

V

CC

Q7

Q6

Q5

Q4

MR

CP

2

3

4

5

6

13

12

11

10

9

DSB

Q0

Q7

Q6

Q5

Q4

MR

Q1

164

Q1

164

Q2

(1)

GND

Q2

Q3

GND

8

001aac828

Transparent top view

001aac422

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 5. Pin conﬁguration SO14 and TSSOP14

Fig 6. Pin conﬁguration DHVQFN14

5.2 Pin description

Table 2.

Symbol

DSA

DSB

Q0

Pin description

1

Description

serial data input A

serial data input B

output 0

2

3

Q1

4

output 1

Q2

5

output 2

Q3

6

output 3

GND

CP

7

ground (0 V)

8

clock input (LOW-to-HIGH edge-triggered)

MR

9

master reset input (active LOW)

Q4

10

11

12

13

14

output 4

Q5

output 5

Q6

output 6

Q7

output 7

V_CC

supply voltage

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

4 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

6. Functional description

Table 3.

Function table^[1]

Operating mode

Control

Input

Output

MR

L

CP

X

DSA

DSB

Q0

L

Q1 to Q7

L to L

Reset (clear)

Shift

X

l

X

l

H

↑

L

q0 to q6

l

h

l

L

h

L

h

H

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

↑ = LOW-to-HIGH transition;

X = don’t care;

q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

−20

−25

-

Max

+7.0

-

Unit

V

supply voltage

input voltage

V

[1]

I_IK

input clamping current

output clamping current

output current

V_I< −0.5 V

mA

°C

I_OK

V_O< −0.5 V or V_O> V_CC+ 0.5 V

V_O= −0.5 V to (V_CC+ 0.5 V)

+20

+25

+75

-

I_O

I_CC

supply current

I_GND

T_stg

P_tot

ground current

−75

−65

-

storage temperature

total power dissipation

+150

500

[2]

T_amb= −40 °C to +125 °C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO14 packages: above 70 °C the value of P_totderates linearly at 8 mW/K.

For TSSOP14 packages: above 60 °C the value of P_totderates linearly at 5.5 mW/K.

For DHVQFN14 packages: above 60 °C the value of P_totderates linearly at 4.5 mW/K.

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

5 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

8. Recommended operating conditions

Table 5.

Symbol

74AHC164

V_CC

Operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

2.0

5.0

5.5

V

V_I

input voltage

0

-

5.5

V

V_O

output voltage

0

-

V_CC

+125

100

20

V

T_amb

ambient temperature

input transition rise and fall rate

−40

+25

°C

ns/V

∆t/∆V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

-

74AHCT164

V_CC

V_I

supply voltage

4.5

0

5.0

5.5

V

input voltage

-

5.5

V

V_O

output voltage

0

-

V_CC

+125

20

V

T_amb

∆t/∆V

ambient temperature

input transition rise and fall rate

−40

-

+25

-

°C

ns/V

V_CC= 4.5 V to 5.5 V

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

74AHC164

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

-

1.5

-

1.5

-

V

V_CC= 3.0 V

2.1

V_CC= 5.5 V

3.85

-

3.85

-

3.85

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

0.9

1.65

-

0.5

0.9

1.65

-

0.5

0.9

1.65

V_CC= 3.0 V

V_CC= 5.5 V

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= −50 µA; V_CC= 2.0 V

I_O= −50 µA; V_CC= 3.0 V

I_O= −50 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 3.0 V

I_O= −8.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

1.9

2.9

2.0

3.0

4.5

-

1.9

2.9

-

1.9

2.9

-

V

4.4

2.58

3.94

2.48

3.80

2.40

3.70

-

V_OL

LOW-level

output voltage

I_O= 50 µA; V_CC= 2.0 V

I_O= 50 µA; V_CC= 3.0 V

I_O= 50 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 3.0 V

I_O= 8.0 mA; V_CC= 4.5 V

-

0

-

0.1

-

0.1

-

0.1

V

0.1

0.36

0.44

0.55

-

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

6 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

I_I

input leakage V_I= 5.5 V or GND;

current _CC= 0 V to 5.5 V

-

0.1

4.0

10

-

1.0

-

2.0

µA

pF

V

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

-

40

-

80

-

V

input

3

capacitance

74AHCT164

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= −50 µA

4.4

4.5

-

4.4

-

4.4

-

V

I_O= −8.0 mA

3.94

3.80

3.70

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 50 µA

-

0

-

0.1

0.36

0.1

-

0.1

0.44

1.0

-

0.1

0.55

2.0

V

I_O= 8.0 mA

V

I_I

input leakage V_I= 5.5 V or GND;

current _CC= 0 V to 5.5 V

-

µA

V

I_CC

∆I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

-

4.0

-

40

-

80

µA

V

additional

per input pin;

1.35

1.5

mA

supply current V_I= V_CC− 2.1 V; I_O= 0 A;

other pins at V_CCor GND;

V

_CC= 4.5 V to 5.5 V

C_I

input

-

3

10

-

pF

capacitance

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

7 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions

74AHC164

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

[2]

t_pd

propagation CP to Qn; see Figure 7

delay

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

6.5 12.8

9.3 16.3

1.0

15.0

18.5

1.0

16.0

20.5

ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.5

9.0

1.0

10.5

12.5

1.0

11.5

14.0

ns

C_L= 50 pF

6.4 11.0

[3]

MR to Qn; see Figure 8

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.3 12.8

7.6 16.3

1.0

15.0

18.5

1.0

16.0

20.5

ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.0

8.6

1.0

10.0

12.0

1.0

11.0

13.5

ns

C_L= 50 pF

5.8 10.6

f_max

maximum

frequency

see Figure 7

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

80

50

125

75

-

65

45

-

50

35

-

MHz

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

125

85

175

115

-

105

75

-

85

65

-

MHz

C_L= 50 pF

t_W

pulse width CP HIGH or LOW;

see Figure 7

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

5.0

-

5.0

-

5.0

-

ns

t_WL

pulse width MR; see Figure 8

LOW

V_CC= 3.0 V to 3.6 V

5.0

-

5.0

-

5.0

-

ns

V_CC= 4.5 V to 5.5 V

t_su

set-up time DSA, DSB to CP;

see Figure 9

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

5.0

4.5

-

6.0

4.5

-

6.0

4.5

-

ns

t_h

hold time

DSA, DSB to CP;

see Figure 9

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

1.5

2.0

-

1.5

2.0

-

1.5

2.0

-

ns

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

8 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions 25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

t_rec

recovery

time

MR to CP; see Figure 8

V_CC= 3.0 V to 3.6 V

2.5

-

2.5

-

2.5

-

ns

pF

V_CC= 4.5 V to 5.5 V

[4]

C_PD

power

f_i= 1 MHz; V_I= GND to V_CC

48

dissipation

capacitance

74AHCT164; V_CC= 4.5 V to 5.5 V

[2]

[3]

t_pd

propagation CP to Qn; see Figure 7

delay

C_L= 15 pF

C_L= 50 pF

-

3.4

9.0

1.0

10.5

12.5

1.0

11.5

14.0

ns

4.9 11.0

MR to Qn; see Figure 8

C_L= 15 pF

-

3.5

8.6

1.0

10.0

12.0

1.0

11.0

13.5

ns

C_L= 50 pF

5.0 10.6

f_max

maximum

frequency

see Figure 7

C_L= 15 pF

125

85

175

115

-

105

75

-

85

65

-

MHz

ns

C_L= 50 pF

t_W

pulse width CP HIGH or LOW;

see Figure 7

5.0

t_WL

t_su

pulse width MR; see Figure 8

LOW

5.0

4.5

2.0

2.5

-

5.0

4.5

2.0

2.5

-

5.0

4.5

2.0

2.5

-

ns

pF

set-up time DSA, DSB to CP;

see Figure 9

t_h

hold time

DSA, DSB to CP;

see Figure 9

-

t_rec

C_PD

recovery

time

MR to CP; see Figure 8

-

[4]

power

f_i= 1 MHz; V_I= GND to V_CC

51

dissipation

capacitance

[1] Typical values are measured at nominal supply voltage (V_CC= 3.3 V and V_CC= 5.0 V).

[2] t_pdis the same as t_PLHand t_PHL

.

[3] t_pdis the same as t_PHLonly.

[4] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

9 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

11. Waveforms

1/f

max

V

I

CP input

V

t

M

GND

t

W

t

PHL

PLH

V

OH

V

Qn output

M

001aac426

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 7. Clock pulse width, maximum frequency and input to output propagation delays

V

I

V

M

MR input

GND

t

rec

WL

V

I

CP input

V

M

GND

t

PHL

V

OH

V

Qn output

M

V

OL

001aac446

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 8. Master reset pulse width, recovery time and propagation delays

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

10 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

V

I

V

CP input

M

GND

t

su

t

h

V

I

V

DSA, DSB input

GND

M

V

OH

V

Qn output

M

V

OL

001aaf612

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 9. Data set-up and hold times

Table 8.

Type

Measurement points

Input

V_M

Output

V_M

74AHC164

0.5 × V_CC

1.5 V

0.5 × V_CC

74AHCT164

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

11 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

t

W

V

I

90 %

negative

pulse

V

M

10 %

GND

t

r

f

t

f

r

V

I

90 %

positive

pulse

M

10 %

GND

t

W

V

CC

V

O

I

G

DUT

R

T

C

L

001aah768

Test data is given in Table 9.

Deﬁnitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

C_L= Load capacitance including jig and probe capacitance

Fig 10. Load circuitry for measuring switching times

Table 9.

Type

Test data

Input

V_I

Load

Test

t_r, t_f

C_L

74AHC164

V_CC

3.0 V

≤ 3.0 ns

15 pF, 50 pF

t_PLH, t_PHL

74AHCT164

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

12 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

v

c

y

H

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

7

e

detail X

w

M

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 11. Package outline SOT108-1 (SO14)

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

13 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

7

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 12. Package outline SOT402-1 (TSSOP14)

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

14 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

6

L

1

7

8

E

h

e

14

13

9

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

1

b

c

E

e

1

y

D

E

L

v

w

y

h

1

max.

0.05 0.30

0.00 0.18

3.1

2.9

1.65

1.35

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT762-1

- - -

MO-241

- - -

Fig 13. Package outline SOT762-1 (DHVQFN14)

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

15 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

ESD

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20080424

Data sheet status

Change notice

Supersedes

74AHC_AHCT164_3

Modiﬁcations:

Product data sheet

-

74AHC_AHCT164_2

• Table 6: the conditions for input leakage current have been changed.

74AHC_AHCT164_2

20061129

Product data sheet

-

74AHC_AHCT164_1

(9397 750 07332)

20000815

Product speciﬁcation

-

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

16 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

74AHC_AHCT164_3

Product data sheet

Rev. 03 — 24 April 2008

17 of 18

74AHC164; 74AHCT164

NXP Semiconductors

8-bit serial-in/parallel-out shift register

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 April 2008

Document identifier: 74AHC_AHCT164_3

型号:	74AHC164PW
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	NXP SEMICONDUCTORS
零件包装代码：	TSSOP
包装说明：	4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
针数：	14
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.23
计数方向：	RIGHT
系列：	AHC/VHC/H/U/V
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e4
长度：	5 mm
逻辑集成电路类型：	SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：	35000000 Hz
湿度敏感等级：	1
位数：	8
功能数量：	1
端子数量：	14
最高工作温度：	125 °C
最低工作温度：	-40 °C
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	2/5.5 V
传播延迟（tpd）：	20.5 ns
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Shift Registers
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
触发器类型：	POSITIVE EDGE
宽度：	4.4 mm
最小 fmax：	85 MHz

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