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    • 北京元坤伟业科技有限公司

           该会员已使用本站17年以上

    • 9DB102BFLFT
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    • QQ:857273081QQ：857273081 复制
      QQ:1594462451QQ：1594462451 复制
    • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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    • 9DB102BFLFT图

    • 集好芯城

       该会员已使用本站13年以上
    • 9DB102BFLFT
    • 数量1068 
    • 厂家Renesas Electronics America Inc. 
    • 封装 
    • 批号最新批次 
    • 原厂原装公司现货
    • QQ:3008092965QQ：3008092965 复制
      QQ:3008092965QQ：3008092965 复制
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    • 9DB102BFLFT图

    • 深圳市惊羽科技有限公司

       该会员已使用本站11年以上
    • 9DB102BFLFT
    • 数量9328 
    • 厂家IDT-集成器 
    • 封装QSOP-20 
    • 批号▉▉：2年内 
    • ▉▉￥12.5元一有问必回一有长期订货一备货HK仓库
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    • 9DB102BFLFT图

    • 万三科技(深圳)有限公司

       该会员已使用本站2年以上
    • 9DB102BFLFT
    • 数量660000 
    • 厂家RENESAS（瑞萨电子） 
    • 封装QSOP-20 
    • 批号23+ 
    • 支持实单/只做原装
    • QQ:3008961398QQ：3008961398 复制
    • 0755-21006672 QQ:3008961398

    产品型号9DB102BFLFT的Datasheet PDF文件预览

    DATASHEET  
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Description  
    Features/Benefits  
    The ICS9DB102 zero-delay buffer supports PCI Express  
    clocking requirements. The ICS9DB102 is driven by a differential  
    SRC output pair from an ICS CK410/CK505-compliant main  
    clock. It attenuates jitter on the input clock and has a selectable  
    PLL Band Width to maximize performance in systems with or  
    without Spread-Spectrum clocking.  
    •
    CLKREQ# pin for outputs 1 and 4/output enable for Express  
    Card applications  
    •
    •
    PLL or bypass mode/PLL can dejitter incoming clock  
    Selectable PLL bandwidth/minimizes jitter peaking in  
    downstream PLL’s  
    •
    Spread Spectrum Compatible/tracks spreading input clock  
    for low EMI  
    •
    •
    SMBus Interface/unused outputs can be disabled  
    Industrial temperature range available  
    Output Features  
    2 - 0.7V current mode differential output pairs (HCSL)  
    •
    Key Specifications  
    Cycle-to-cycle jitter < 35ps  
    •
    •
    Output-to-output skew < 25ps  
    Functional Block Diagram  
    CLKREQ0#  
    CLKREQ1#  
    PCIEX0  
    PCIEX1  
    CLK_INT  
    SPREAD  
    COMPATIBLE  
    PLL  
    CLK_INC  
    PLL_BW  
    SMBDAT  
    SMBCLK  
    CONTROL  
    LOGIC  
    IREF  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    1
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Pin Configuration  
    Power Groups  
    Pin Number  
    PLL_BW 1  
    CLK_INT 2  
    CLK_INC 3  
    20 VDDA  
    19 GNDA  
    Description  
    VDD  
    GND  
    5,9,12,16  
    9
    6,15  
    6
    PCI Express Outputs  
    SMBUS  
    IREF  
    18 IREF  
    17 **CLKREQ1#  
    4
    5
    **CLKREQ0#  
    VDD  
    20  
    20  
    19  
    19  
    Analog VDD & GND for PLL core  
    16  
    15 GND  
    VDD  
    GND 6  
    7
    14  
    13  
    PCIEXT0  
    PCIEXC0  
    VDD  
    PCIEXT1  
    PCIEXC1  
    8
    9
    10  
    12 VDD  
    11 SMBCLK  
    SMBDAT  
    Note: Pins preceeded by '**' have internal  
    120K ohm pull down resistors  
    20-pin SSOP & TSSOP  
    Pin Description  
    PIN #  
    PIN NAME  
    PIN TYPE  
    DESCRIPTION  
    3.3V input for selecting PLL Band Width  
    0 = low, 1= high  
    1
    PLL_BW  
    INPUT  
    2
    3
    CLK_INT  
    CLK_INC  
    INPUT  
    INPUT  
    "True" reference clock input.  
    "Complementary" reference clock input.  
    Output enable for SRC/PCI Express output pair '0'  
    0 = enabled, 1 = tri-stated  
    4
    **CLKREQ0#  
    INPUT  
    5
    VDD  
    POWER  
    POWER  
    OUTPUT  
    OUTPUT  
    POWER  
    I/O  
    Power supply, nominal 3.3V  
    6
    GND  
    Ground pin.  
    7
    PCIEXT0  
    PCIEXC0  
    VDD  
    True clock of differential PCI_Express pair.  
    8
    Complement clock of differential PCI_Express pair.  
    Power supply, nominal 3.3V  
    9
    10  
    11  
    12  
    13  
    14  
    15  
    16  
    SMBDAT  
    SMBCLK  
    VDD  
    Data pin of SMBUS circuitry, 5V tolerant  
    Clock pin of SMBUS circuitry, 5V tolerant  
    Power supply, nominal 3.3V  
    INPUT  
    POWER  
    OUTPUT  
    OUTPUT  
    POWER  
    POWER  
    PCIEXC1  
    PCIEXT1  
    GND  
    Complement clock of differential PCI_Express pair.  
    True clock of differential PCI_Express pair.  
    Ground pin.  
    VDD  
    Power supply, nominal 3.3V  
    Output enable for SRC/PCI Express output pair '1'  
    0 = enabled, 1 = tri-stated  
    17  
    **CLKREQ1#  
    IREF  
    INPUT  
    This pin establishes the reference current for the differential current-  
    mode output pairs. This pin requires a fixed precision resistor tied to  
    ground in order to establish the appropriate current. 475 ohms is the  
    standard value.  
    18  
    OUTPUT  
    19  
    20  
    GNDA  
    VDDA  
    POWER  
    POWER  
    Ground pin for the PLL core.  
    3.3V power for the PLL core.  
    Note:  
    Pins preceeded by '**' have internal 120K ohm pull down resistors  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    2
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Absolute Max  
    Symbol  
    VDDA  
    VDD  
    Parameter  
    Min  
    Max  
    Units  
    3.3V Core Supply Voltage  
    3.3V Output Supply Voltage  
    VDD + 0.5V  
    VDD + 0.5V  
    V
    GND - 0.5  
    -65  
    V
    Ts  
    Storage Temperature  
    Case Temperature  
    Input ESD protection  
    human body model  
    150  
    115  
    °C  
    °C  
    Tcase  
    ESD prot  
    2000  
    V
    Electrical Characteristics - Input/Supply/Common Output Parameters  
    TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%  
    PARAMETER  
    SYMBOL  
    CONDITIONS  
    MIN  
    TYP  
    MAX  
    UNITS NOTES  
    Tambcom  
    Tambind  
    Commercial range  
    Industrial range  
    0
    70  
    85  
    °C  
    °C  
    1
    1
    Tambient  
    -40  
    Input High Voltage  
    VIH  
    3.3 V +/-5%  
    2
    VDD + 0.3  
    V
    1
    Input Low Voltage  
    Input High Current  
    VIL  
    IIH  
    3.3 V +/-5%  
    VIN = VDD  
    VSS - 0.3  
    -5  
    0.8  
    5
    V
    1
    1
    uA  
    VIN = 0 V; Inputs with no pull-  
    up resistors  
    IIL1  
    IIL2  
    -5  
    uA  
    uA  
    1
    1
    Input Low Current  
    VIN = 0 V; Inputs with pull-up  
    resistors  
    -200  
    75  
    27  
    Full Active, CL = Full load;  
    all differential pairs tri-stated  
    VDD = 3.3 V  
    100  
    50  
    105  
    7
    mA  
    mA  
    MHz  
    nH  
    1
    1
    1
    1
    1
    1
    Operating Supply Current  
    IDD3.3OP  
    Input Frequency3  
    Pin Inductance1  
    Fi  
    80  
    100  
    Lpin  
    CIN  
    Logic Inputs  
    5
    pF  
    Input Capacitance1  
    Clk Stabilization1,2  
    COUT  
    Output pin capacitance  
    4.5  
    pF  
    From VDD Power-Up to 1st  
    clock  
    TSTAB  
    1.8  
    33  
    45  
    ms  
    kHz  
    KHz  
    1
    1
    1
    Modulation Frequency  
    Spread Spectrum Modulation  
    Frequency  
    Triangular Modulation  
    30  
    25  
    fMOD  
    Lexmark Modulation  
    PLL Bandwidth when  
    PLL_BW=0  
    400  
    1.2  
    KHz  
    MHz  
    1
    1
    PLL Bandwidth  
    BW  
    VDD  
    PLL Bandwidth when  
    PLL_BW=1  
    SMBus Voltage  
    2.7  
    4
    5.5  
    0.4  
    V
    V
    1
    1
    1
    Low-level Output Voltage  
    VOLSMBUS @ IPULLUP  
    IPULLUP SMBus SDATA pin  
    Current sinking at VOL = 0.4 V  
    SCLK/SDATA  
    mA  
    TRI2C  
    (Max VIL - 0.15) to (Min VIH + 0.15)  
    1000  
    300  
    ns  
    ns  
    1
    1
    Clock/Data Rise Time  
    SCLK/SDATA  
    TFI2C  
    (Min VIH + 0.15) to (Max VIL - 0.15)  
    Clock/Data Fall Time  
    1Guaranteed by design and characterization, not 100% tested in production.  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    3
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair  
    Ω
    Ω
    Ω
    TA = Tambient; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 , IREF = 475  
    PARAMETER  
    Current Source Output  
    Impedance  
    SYMBOL  
    Zo  
    CONDITIONS  
    MIN  
    TYP  
    MAX  
    UNITS NOTES  
    Ω
    VO = Vx  
    3000  
    1
    Voltage High  
    VHigh  
    VLow  
    Vovs  
    Vuds  
    Statistical measurement on  
    single ended signal using  
    660  
    850  
    150  
    1,3  
    1,3  
    1,3  
    1,3  
    mV  
    mV  
    mV  
    mV  
    Voltage Low  
    -150  
    Max Voltage  
    Measurement on single ended  
    signal using absolute value.  
    1150  
    Min Voltage  
    -300  
    250  
    Crossing Voltage (abs) Vcross(abs)  
    Crossing Voltage (var) d-Vcross  
    350  
    12  
    550  
    140  
    1,3  
    1,3  
    Variation of crossing over all  
    edges  
    Long Accuracy  
    Average period  
    ppm  
    see Tperiod min-max values  
    100.00MHz nominal  
    0
    ppm  
    ns  
    1,2  
    2
    9.9970  
    9.9970  
    9.8720  
    175  
    10.0030  
    10.0533  
    Tperiod  
    100.00MHz spread  
    ns  
    2
    Absolute min period  
    Rise Time  
    Tabsmin  
    100.00MHz nominal/spread  
    VOL = 0.175V, VOH = 0.525V  
    ns  
    1,2  
    1
    tr  
    tf  
    700  
    700  
    125  
    125  
    150  
    4.2  
    ps  
    Fall Time  
    VOH = 0.525V VOL = 0.175V  
    175  
    ps  
    ps  
    ps  
    ps  
    ns  
    1
    1
    1
    1
    1
    Rise Time Variation  
    Fall Time Variation  
    d-tr  
    d-tf  
    tpd  
    30  
    30  
    PLL Mode.  
    0
    Input to Output Delay  
    tpdbyp  
    Bypass mode  
    Measurement from differential  
    wavefrom  
    3.7  
    Duty Cycle  
    dt3  
    45  
    55  
    25  
    %
    1
    1
    Output-to-Output Skew  
    tsk3  
    VT = 50%  
    ps  
    PLL mode. Measurement from  
    differential wavefrom  
    tjcyc-cyc  
    35  
    30  
    ps  
    ps  
    1
    1
    Jitter, Cycle to cycle  
    tjcyc-cycbyp  
    Additve Jitter in Bypass Mode  
    1Guaranteed by design, not 100% tested in production.  
    2 The 9DB102 does not add a ppm error to the input clock  
    .
    3IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .  
    Ω
    Ω
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    4
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Electrical Characteristics - PLL Parameters  
    TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%  
    Group  
    Parameter  
    Description  
    Min Typ Max Units  
    Notes  
    PLL Jitter Peaking jpeak-hibw  
    PLL Jitter Peaking jpeak-lobw  
    (PLL_BW = 1)  
    0
    0
    1
    1
    2.5  
    2
    dB  
    dB  
    1,4  
    (PLL_BW = 0)  
    (PLL_BW = 1)  
    1,4  
    PLL Bandwidth  
    PLL Bandwidth  
    pllHIBW  
    pllLOBW  
    2
    2.5  
    0.5  
    3
    1
    MHz  
    MHz  
    1,5  
    1,5  
    (PLL_BW = 0)  
    PCIe Gen 1 phase jitter  
    (1.5 - 22 MHz)  
    0.4  
    40  
    108  
    ps  
    1,2,3  
    PCIe Gen 2 jitter  
    (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz  
    (PLL_BW=1)  
    2.7  
    3.1 ps rms  
    3.1 ps rms  
    1,2,3  
    Jitter, Phase  
    tjphasePLL  
    PCIe Gen 2 jitter  
    (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz  
    (PLL_BW=0)  
    2.2  
    1.3  
    1,2,3  
    1,2,3  
    PCIe Gen 2 jitter  
    3
    ps rms  
    (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz  
    NOTES:  
    1. Guaranteed by design and characterization, not 100% tested in production.  
    2. See http://www.pcisig.com for complete specs  
    3. Device driven by 932S421BGLF or equivalent  
    Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.  
    Measured at 3 db dow n or half pow er point.  
    4.  
    5.  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    5
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    SRC Reference Clock  
    Common Recommendations for Differential Routing  
    Dimension or Value  
    0.5 max  
    Unit Figure  
    L1 length, route as non-coupled 50ohm trace  
    inch  
    inch  
    inch  
    ohm  
    ohm  
    1
    1
    1
    1
    1
    L2 length, route as non-coupled 50ohm trace  
    0.2 max  
    0.2 max  
    33  
    L3 length, route as non-coupled 50ohm trace  
    Rs  
    Rt  
    49.9  
    Down Device Differential Routing  
    L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max  
    inch  
    inch  
    1
    1
    L4 length, route as coupled stripline 100ohm differential trace  
    1.8 min to 14.4 max  
    Differential Routing to PCI Express Connector  
    L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max  
    inch  
    inch  
    2
    2
    L4 length, route as coupled stripline 100ohm differential trace  
    0.225 min to 12.6 max  
    Figure 1: Down Device Routing  
    L2  
    L1  
    Rs  
    Rs  
    L4  
    L4'  
    L2'  
    L1'  
    Rt  
    Rt  
    HCSL Output Buffer  
    PCI Express  
    Down Device  
    REF_CLK Input  
    L3' L3  
    Figure 2: PCI Express Connector Routing  
    L2  
    L1  
    Rs  
    L4  
    L4'  
    L2'  
    L1'  
    Rs  
    Rt  
    Rt  
    HCSL Output Buffer  
    PCI Express  
    Add-in Board  
    REF_CLK Input  
    L3' L3  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    6
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Alternative Termination for LVDS and other Common Differential Signals (figure 3)  
    Vdiff  
    0.45v  
    0.58  
    0.80  
    0.60  
    Vp-p  
    0.22v  
    0.28  
    0.40  
    0.3  
    Vcm  
    1.08  
    0.6  
    R1  
    33  
    33  
    33  
    33  
    R2  
    R3  
    R4  
    Note  
    150  
    78.7  
    78.7  
    174  
    100  
    137  
    none  
    140  
    100  
    100  
    100  
    100  
    0.6  
    ICS874003i-02 input compatible  
    Standard LVDS  
    1.2  
    R1a = R1b = R1  
    R2a = R2b = R2  
    Figure 3  
    L2  
    L1  
    R3  
    R4  
    R1a  
    L4  
    L4'  
    L2'  
    L1'  
    R1b  
    R2a  
    R2b  
    HCSL Output Buffer  
    Down Device  
    REF_CLK Input  
    L3'  
    L3  
    Cable Connected AC Coupled Application (figure 4)  
    Component  
    R5a, R5b  
    R6a, R6b  
    Cc  
    Value  
    Note  
    8.2K 5%  
    1K 5%  
    0.1 µF  
    Vcm  
    0.350 volts  
    Figure 4  
    3.3 Volts  
    R5a  
    R5b  
    R6b  
    Cc  
    L4  
    L4'  
    Cc  
    R6a  
    PCIe Device  
    REF_CLK Input  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    7
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    General SMBus serial interface information for the ICS9DB102  
    How to Write:  
    • Controller (host) sends a start bit.  
    How to Read:  
    • Controller (host) will send start bit.  
    • Controller (host) sends the write address D4(h)  
    • ICS clock will acknowledge  
    • Controller (host) sends the write address D4(h)  
    • ICS clock will acknowledge  
    • Controller (host) sends the begining byte location = N  
    • ICS clock will acknowledge  
    • Controller (host) sends the begining byte  
    location = N  
    • Controller (host) sends the data byte count = X  
    • ICS clock will acknowledge  
    • ICS clock will acknowledge  
    • Controller (host) will send a separate start bit.  
    • Controller (host) sends the read address D5(h)  
    • ICS clock will acknowledge  
    • Controller (host) starts sending Byte N through  
    Byte N + X -1  
    • ICS clock will acknowledge each byte one at a time  
    • ICS clock will send the data byte count = X  
    • ICS clock sends Byte N + X -1  
    • Controller (host) sends a Stop bit  
    • ICS clock sends Byte 0 through byte X (if X(h)  
    was written to byte 8).  
    • Controller (host) will need to acknowledge each byte  
    • Controllor (host) will send a not acknowledge bit  
    • Controller (host) will send a stop bit  
    Index Block Read Operation  
    Controller (Host)  
    Index Block Write Operation  
    ICS (Slave/Receiver)  
    ICS (Slave/Receiver)  
    Controller (Host)  
    starT bit  
    T
    starT bit  
    T
    Slave Address D4(h)  
    Slave Address D4(h)  
    WR  
    WRite  
    WR  
    WRite  
    ACK  
    ACK  
    ACK  
    ACK  
    ACK  
    ACK  
    Beginning Byte = N  
    Beginning Byte = N  
    Data Byte Count = X  
    Beginning Byte N  
    RT  
    Repeat starT  
    Slave Address D5(h)  
    RD  
    ReaD  
    ACK  
    Data Byte Count = X  
    Beginning Byte N  
    ACK  
    ACK  
    Byte N + X - 1  
    ACK  
    P
    stoP bit  
    Byte N + X - 1  
    N
    P
    Not acknowledge  
    stoP bit  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    8
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)  
    Byte 0  
    Pin #  
    Name  
    Control Function Type  
    0
    1
    PWD  
    Functions  
    controlled by  
    SMBus  
    Functions  
    controlled by  
    device pins  
    Enables SMBus  
    RW  
    Control  
    -
    SW_EN  
    1
    Bit 7  
    registers  
    -
    -
    -
    -
    -
    RESERVED  
    RESERVED  
    RW  
    RW  
    RW  
    RW  
    RW  
    -
    -
    -
    -
    -
    X
    X
    X
    X
    X
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    RESERVED  
    RESERVED  
    RESERVED  
    Selects PLL  
    -
    -
    PLL BW #adjust  
    PLL Enable  
    RW  
    RW  
    Low BW  
    High BW  
    1
    1
    Bit 1  
    Bit 0  
    Bandwidth  
    Bypasses PLL for  
    board test  
    PLL bypassed PLL enabled  
    (fan out mode) (ZDB mode)  
    SMBus Table: Output Enable Register  
    Byte 1 Pin # Name  
    Bit 7  
    Control Function Type  
    0
    1
    PWD  
    X
    -
    -
    -
    -
    -
    -
    -
    -
    RESERVED  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    -
    -
    -
    -
    -
    -
    -
    -
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    X
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    Bit 1  
    Bit 0  
    X
    X
    X
    X
    X
    X
    SMBus Table: Function Select Register  
    Byte 2 Pin # Name  
    Bit 7  
    Control Function Type  
    0
    1
    PWD  
    X
    RESERVED  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    -
    -
    -
    -
    -
    -
    -
    -
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    RESERVED  
    X
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    Bit 1  
    Bit 0  
    -
    -
    -
    -
    -
    -
    X
    X
    X
    X
    X
    X
    SMBus Table: Vendor & Revision ID Register  
    Byte 3  
    Bit 7  
    Pin #  
    Name  
    RID3  
    RID2  
    RID1  
    RID0  
    VID3  
    VID2  
    VID1  
    VID0  
    Control Function Type  
    0
    -
    -
    -
    -
    -
    -
    -
    -
    1
    -
    -
    -
    -
    -
    -
    -
    -
    PWD  
    -
    -
    -
    -
    -
    -
    -
    -
    R
    0
    0
    0
    1
    0
    0
    0
    1
    R
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    Bit 1  
    Bit 0  
    REVISION ID  
    R
    R
    R
    R
    VENDOR ID  
    R
    R
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    9
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    SMBus Table: DEVICE ID  
    Byte 4  
    Bit 7  
    Pin #  
    Name  
    Control Function Type  
    0
    1
    PWD  
    -
    -
    -
    -
    -
    -
    -
    -
    R
    R
    R
    -
    -
    -
    -
    -
    -
    -
    -
    0
    0
    0
    0
    0
    1
    1
    0
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    Bit 1  
    Bit 0  
    Device ID  
    = 06 Hex  
    R
    R
    R
    R
    R
    SMBus Table: Byte Count Register  
    Control  
    Byte 5  
    Pin #  
    Name  
    Type  
    0
    1
    PWD  
    Function  
    -
    -
    -
    -
    -
    -
    -
    -
    BC7  
    BC6  
    BC5  
    BC4  
    BC3  
    BC2  
    BC1  
    BC0  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    RW  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    0
    0
    0
    0
    0
    1
    1
    0
    Bit 7  
    Writing to this  
    register will  
    Bit 6  
    Bit 5  
    Bit 4  
    Bit 3  
    Bit 2  
    Bit 1  
    Bit 0  
    configure how  
    many bytes will be  
    read back, default  
    is 06 = 6 bytes.  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    10  
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    20-Pin SSOP Package Drawing and Dimensions  
    20-Lead, 150 mil SSOP (QSOP)  
    In Millimeters  
    In Inches  
    SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS  
    MIN  
    1.35  
    0.10  
    --  
    MAX  
    1.75  
    0.25  
    1.50  
    0.30  
    0.25  
    MIN  
    .053  
    .004  
    --  
    MAX  
    .069  
    .010  
    .059  
    .012  
    .010  
    A
    A1  
    A2  
    b
    0.20  
    0.18  
    .008  
    .007  
    c
    D
    SEE VARIATIONS  
    SEE VARIATIONS  
    E
    5.80  
    3.80  
    6.20  
    4.00  
    .228  
    .150  
    .244  
    .157  
    E1  
    e
    0.635 BASIC  
    0.025 BASIC  
    L
    0.40  
    1.27  
    .016  
    .050  
    N
    SEE VARIATIONS  
    0° 8°  
    SEE VARIATIONS  
    SEE VARIATIONS  
    0° 8°  
    SEE VARIATIONS  
    a
    ZD  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    11  
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    20-Pin TSSOP Package Drawing and Dimensions  
    20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP  
    c
    N
    (173 mil)  
    (25.6 mil)  
    In Inches  
    In Millimeters  
    SYMBOL  
    COMMON DIMENSIONS COMMON DIMENSIONS  
    L
    MIN  
    --  
    MAX  
    1.20  
    0.15  
    1.05  
    0.30  
    0.20  
    MIN  
    --  
    MAX  
    .047  
    .006  
    .041  
    .012  
    .008  
    A
    A1  
    A2  
    b
    E1  
    E
    0.05  
    0.80  
    0.19  
    0.09  
    .002  
    .032  
    .007  
    .0035  
    INDEX  
    AREA  
    c
    D
    SEE VARIATIONS  
    6.40 BASIC  
    SEE VARIATIONS  
    0.252 BASIC  
    1
    2
    E
    α
    E1  
    e
    4.30  
    4.50  
    .169  
    .177  
    D
    0.65 BASIC  
    0.0256 BASIC  
    L
    0.45  
    0.75  
    .018  
    .030  
    N
    SEE VARIATIONS  
    SEE VARIATIONS  
    a
    0°  
    --  
    8°  
    0°  
    --  
    8°  
    A
    A2  
    aaa  
    0.10  
    .004  
    A1  
    VARIATIONS  
    - C -  
    SEATING  
    D mm.  
    D (inch)  
    N
    e
    MIN  
    6.40  
    MAX  
    6.60  
    MIN  
    .252  
    MAX  
    .260  
    b
    PLANE  
    20  
    aaa C  
    Reference Doc.: JEDEC Publication 95, MO-153  
    10-0035  
    Ordering Information  
    Part / Order Number Shipping Packaging  
    Package  
    Temperature  
    0 to +70°C  
    9DB102BFLF  
    9DB102BFLFT  
    9DB102BFILF  
    9DB102BFILFT  
    9DB102BGLF  
    9DB102BGLFT  
    9DB102BGILF  
    9DB102BGILFT  
    Tubes  
    Tape and Reel  
    Tubes  
    20-pin SSOP  
    20-pin SSOP  
    20-pin SSOP  
    20-pin SSOP  
    20-pin TSSOP  
    20-pin TSSOP  
    20-pin TSSOP  
    20-pin TSSOP  
    0 to +70°C  
    -40 to +85°C  
    -40 to +85°C  
    0 to +70°C  
    Tape and Reel  
    Tubes  
    Tape and Reel  
    Tubes  
    0 to +70°C  
    -40 to +85°C  
    -40 to +85°C  
    Tape and Reel  
    "LF" after the package code are the Pb-Free configuration and are RoHS compliant.  
    "B" is the device revision designator (will not correlate to the datasheet revision).  
    IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
    852 REV K 04/01/10  
    12  
    ICS9DB102  
    Two Output Differential Buffer for PCIe Gen1 & Gen2  
    Revision History  
    Rev. Originator Issue Date Description  
    1. Added Phase Noise Parameters, Updated input to output delay values.  
    2. PLL BW moved to PLL parameters table.  
    8/6/2007 3. Added terminations tables.  
    F
    G
    H
    12/14/2007 Updated General SMBus Interface Information.  
    10/29/2008 Corrected "HCSL" typos.  
    1. Added I-temp electricals  
    2. Changed datasheet title  
    1/15/2010  
    J
    3. Updated Input Frequency parameter  
    4. Updated ordering information  
    K
    RW  
    4/1/2010 Updated ordering info for Rev B  
    Innovate with IDT and accelerate your future networks. Contact:  
    www.IDT.com  
    For Sales  
    800-345-7015  
    408-284-8200  
    Fax: 408-284-2775  
    For Tech Support  
    408-284-6578  
    pcclockhelp@idt.com  
    Corporate Headquarters  
    Asia Pacific and Japan  
    Europe  
    Integrated Device Technology, Inc.  
    6024 Silver Creek Valley Road  
    San Jose, CA 95138  
    United States  
    800 345 7015  
    +408 284 8200 (outside U.S.)  
    IDT Singapore Pte. Ltd.  
    1 Kallang Sector #07-01/06  
    KolamAyer Industrial Park  
    Singapore 349276  
    Phone: 65-6-744-3356  
    Fax: 65-6-744-1764  
    IDT Europe Limited  
    321 Kingston Road  
    Leatherhead, Surrey  
    KT22 7TU  
    England  
    Phone: 44-1372-363339  
    Fax: 44-1372-378851  
    ©
    of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks  
    2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks  
    a
    are or may be trademarks or registered trademarks used to identify products or services of their respective owners.  
    Printed in USA  
    配单直通车
    9DB102BFLFT产品参数
    型号:9DB102BFLFT
    Brand Name：Integrated Device Technology
    是否无铅：不含铅
    是否Rohs认证：符合
    生命周期：Obsolete
    IHS 制造商：INTEGRATED DEVICE TECHNOLOGY INC
    零件包装代码：QSOP
    包装说明：SSOP-20
    针数：20
    制造商包装代码：PCG20
    Reach Compliance Code：compliant
    ECCN代码：EAR99
    HTS代码：8542.39.00.01
    风险等级：5.62
    Is Samacsys：N
    系列：9DB
    输入调节：DIFFERENTIAL
    JESD-30 代码：R-PDSO-G20
    JESD-609代码：e3
    长度：8.65 mm
    逻辑集成电路类型：PLL BASED CLOCK DRIVER
    湿度敏感等级：1
    功能数量：1
    反相输出次数：
    端子数量：20
    实输出次数：2
    最高工作温度：70 °C
    最低工作温度：
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：SSOP
    封装等效代码：SSOP20,.25
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, SHRINK PITCH
    峰值回流温度（摄氏度）：260
    电源：3.3 V
    Prop。Delay @ Nom-Sup：0.185 ns
    传播延迟（tpd）：0.15 ns
    认证状态：Not Qualified
    Same Edge Skew-Max（tskwd）：0.025 ns
    座面最大高度：1.75 mm
    子类别：Clock Drivers
    最大供电电压 (Vsup)：3.465 V
    最小供电电压 (Vsup)：3.135 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    温度等级：COMMERCIAL
    端子面层：Matte Tin (Sn) - annealed
    端子形式：GULL WING
    端子节距：0.635 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：3.9 mm
    Base Number Matches：1
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