Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Memory Read Timing – Asynchronous Mode
CLK
ADDRLAT
MEMREQn
MEMGNTn
MEMCEN
MEMDEN
MEMCSn
MEMADDR
MEMOPER
Valid Address
Valid Operation
MEMDATA
MEMRDn
Data
MEMWAITn
Figure 12 • Memory Read Timing – Asynchronous Mode
Memory Read Timing
Table 15 • Memory Read Timing
Async Mode
TpwRD
Description
Time
Read pulse width (no wait states)
1 clock cycle
1.2 µs
TpdGNT
Maximum delay from MEMREQn to MEMGNTn active
Address setup time to MEMRDn low
Address hold time from MEMRDn high
Wait setup to rising clock edge
TsuADDR
ThdADDR
TsuWAIT
1 clock cycle
1 clock cycle
TsuDATA
Data setup time to MEMRDn high
Advanced v1.1
21
ACTEL [ Actel Corporation ]
