Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Transceiver Loopback Delays
Core1553BRT-EBR verifies that all transmitted data words
are correctly transmitted. As data is transmitted by the
transceiver on the 1553EBR bus, it is monitored by the
transceiver and decoded by Core1553BRT-EBR. The core
requires that the loopback delay, i.e., the time from
BUSAOUT to BUSAIN, be less than 180 ns.
The loopback delay is a function of the internal FPGA
delay, PCB routing delays, internal transceiver delay, and
transmission effects from the 1553EBR bus. Additional
register stages may be inserted on either the 1553EBR
data input or output within the FPGA, providing the
required loopback delay is not violated.
Ordering Information
Core1553BRT-EBR can be ordered through your local
Actel sales representative. It should be ordered using the
following number scheme: Core1553BRT-EBR-XX, where
XX is listed in
Table 18 •
Ordering Codes
XX
EV
SN
AN
SR
AR
UR
Evaluation version
Netlist for single-use on Actel devices
Netlist for unlimited use on Actel devices
RTL for single-use on Actel devices
RTL for unlimited use on Actel devices
RTL for unlimited use and not restricted to Actel devices
Description
Clock Requirements
To meet 1553EBR transmission bit rate requirements, the
Core1553BRT-EBR clock input must be 100 MHz ±0.01%.
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
Advanced v1.0
Changes in Current Version (A dv anced v 1 .1 )
The product name was changed from Core1553EBRRT to Core1553BRT-EBR.
Changed "MIL-STD-1553EBR" to "MIL-STD-1553B" under
First bullet added under
Changed "SAE AIR5610" to "SAE AS5682" under
Changed Time values in
Changed maximum loopback delay under
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A d v an c ed v1 . 1
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ACTEL [ Actel Corporation ]
