AD7224
BIP O LAR O UTP UT O P ERATIO N
V
IN
V
V
REF
DD
T he AD7224 can be configured to provide bipolar output op-
eration using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
V
OUT
AGND
DAC
V
IN
R2
R1
R2
R1
VO = 1 +
With R1 = R2
• D V
(
–
• V
(
REF
)
)
REF
V
AD7224
BIAS
V
DGND
SS
VO = (2 D – 1) • VREF
where D is a fractional representation of the digital word in
the DAC register.
Figure 7. AGND Bias Circuit
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over tempera-
ture. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. T able III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
MICRO P RO CESSO R INTERFACE
A15
ADDRESS BUS
A8
CS
ADDRESS
8085A
DECODE
8088
LDAC
AD7224*
WR
WR
V
REF
LATCH
V
V
REF
DB7
DB0
DD
R1
EN
R2
ALE
3
DB7
AD7
+15V
ADDRESS DATA BUS
DATA
(8-BIT)
AD0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
V
DB0
CS
OUT
DAC
V
Figure 8. AD7224 to 8085A/8088 Interface
OUT
+15V
WR
LDAC
RESET
A15
AD7224
R1, R2 = 10kΩ ±0.1%
ADDRESS BUS
A0
AGND
DGND
6809
6502
V
SS
CS
ADDRESS
DECODE
LDAC
EN
R/W
AD7224*
Figure 6. Bipolar Output Circuit
E OR φ2
WR
D7
E OR φ2
D0
Table III. Bipolar (O ffset Binary) Code Table
D AC Register Contents
DB7
DB0
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
MSB
LSB
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
Analog O utput
127
+VREF
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
Figure 9. AD7224 to 6809/6502 Interface
128
1
+VREF
A15
128
ADDRESS BUS
A0
0 V
CS
Z-80
ADDRESS
DECODE
LDAC
1
–VREF
AD7224*
WR
128
WR
127
–VREF
DB7
DB0
128
D7
D0
DATA BUS
128
128
–VREF
= –VREF
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 10. AD7224 to Z-80 Interface
AGND BIAS
T he AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. T he output voltage, VOUT , is expressed as:
A23
ADDRESS BUS
A1
68008
CS
ADDRESS
DECODE
LDAC
WR
VOUT = VBIAS + D • (VIN)
R/W
DTACK
AD7224*
DB7
where D is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
DB0
D7
D0
For a given VIN, increasing AGND above system GND will re-
duce the effective VDD–VREF which must be at least 4 V to en-
sure specified operation. Note that VDD and VSS for the AD7224
must be referenced to DGND.
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 11. AD7224 to 68008 Interface
–7–
REV. B
ADI [ ADI ]
