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AD1674JN 参数 Datasheet PDF下载

AD1674JN图片预览
型号: AD1674JN
PDF下载: 下载PDF文件 查看货源
内容描述: 12位100 kSPS的A / D转换器 [12-Bit 100 kSPS A/D Converter]
分类和应用: 转换器模数转换器光电二极管信息通信管理
文件页数/大小: 12 页 / 257 K
品牌: AD [ ANALOG DEVICES ]
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AD1674
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
Parameter
Conversion Time
8-Bit Cycle
12-Bit Cycle
STS Delay from CE
CE Pulse Width
CS
to CE Setup
CS
Low During CE High
R/C to CE Setup
R/C Low During CE High
A
0
to CE Setup
A
0
Valid During CE High
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
t
C
t
C
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
7
9
50
50
50
50
50
0
50
8
10
200
50
50
50
50
50
0
50
7
9
8
µs
10
µs
225 ns
ns
ns
ns
ns
ns
ns
ns
t
HEC
t
HSC
t
SSC
t
SRC
t
HRC
(for all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= –15 V 10% or –12 V 5%; V
IL
= 0.4 V,
V
IH
= 2.4 V unless otherwise noted)
CE
__
CS
_
R/C
A
0
t
SAC
t
HAC
t
C
STS
DB11 – DB0
t
DSC
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
Access Time
Data Valid After CE Low
Output Float Delay
CS
to CE Setup
R/C to CE Setup
A
0
to CE Setup
CS
Valid After CE Low
R/C High After CE Low
A
0
Valid After CE Low
J, K, A, B, Grades
T Grade
Symbol Min Typ Max Min Typ Max Units
t
DD1
t
HD
t
HL5
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
75
25
2
20
3
150
50
0
50
0
0
50
50
0
50
0
0
50
150
25
2
15
4
75
150 ns
ns
ns
150 ns
ns
ns
ns
ns
ns
ns
HIGH IMPEDANCE
Figure 1. Converter Start Timing
CE
__
CS
t
SSR
_
R/C
t
HSR
t
SSR
t
HRR
A
0
t
SAR
t
HS
NOTES
1
t
DD
is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0°C to T
MAX
.
3
At –40°C.
4
At –55°C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
t
HAR
STS
t
HD
DB11 – DB0
HIGH
IMPEDANCE
DATA
VALID
HIGH
IMP.
t
DD
t
HL
Figure 2. Read Timing
Test
Access Time High Z to Logic Low
Float Time Logic High to High Z
Access Time High Z to Logic High
Float Time Logic Low to High Z
V
CP
5V
0V
0V
5V
C
OUT
100 pF
10 pF
100 pF
10 pF
D
OUT
C
OUT
I
OL
V
CP
I
OH
Figure 3. Load Circuit for Bus Timing Specifications
REV. C
–5–