Typical Dynamic Performance–AD1674
80
f
SAMPLE
= 100kSPS
FULL-SCALE = +10V
0
S/(N+D) – dB
70
60
0dB INPUT
–20dB INPUT
–20
AMPLITUDE – dB
THD
–40
–60
–80
–100
–120
1
10
100
1000
10000
INPUT FREQUENCY – kHz
3
RD
HARMONIC
2
ND
HARMONIC
50
40
30
20
–60dB INPUT
10
0
1
10
100
1000
10000
INPUT FREQUENCY – kHz
Figure 5. Harmonic Distortion vs.
Input Frequency
0
–20
Figure 6. S/(N+D) vs. Input Frequency
and Amplitude
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15
Figure 7. S/(N+D) vs. Input Amplitude
AMPLITUDE – dB
–40
–60
–80
–100
–120
–140
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – kHz
AMPLITUDE – dB
Figure 8. Nonaveraged 2048 Point FFT
at 100 kSPS, f
IN
= 25.049 kHz
GENERAL CIRCUIT OPERATION
30
20
25
FREQUENCY – kHz
35
40
45
50
Figure 9. IMD Plot for f
IN
= 9.08 kHz (fa), 9.58 kHz (fb)
The AD1674 is a complete 12-bit, 10
µs
sampling analog-to-
digital converter. A block diagram of the AD1674 is shown on
page 7.
When the control section is commanded to initiate a conversion
(as described later), it places the sample-and-hold amplifier
(SHA) in the hold mode, enables the clock, and resets the suc-
cessive approximation register (SAR). Once a conversion cycle
has begun, it cannot be stopped or restarted and data is not
available from the output buffers. The SAR, timed by the inter-
nal clock, will sequence through the conversion cycle and return
an end-of-convert flag to the control section when the conver-
sion has been completed. The control section will then disable
the clock, switch the SHA to sample mode, and delay the STS
LOW going edge to allow for acquisition to 12-bit accuracy.
The control section will allow data read functions by external
command anytime during the SHA acquisition interval.
During the conversion cycle, the internal 12-bit, 1 mA full-scale
current output DAC is sequenced by the SAR from the most
significant bit (MSB) to the least significant bit (LSB) to pro-
vide an output that accurately balances the current through the
5 kΩ resistor from the input signal voltage held by the SHA.
The SHA’s input scaling resistors divide the input voltage by 2
for the 10 V input span and by 4 V for the 20 V input span,
maintaining a 1 mA full-scale output current through the 5 kΩ
resistor for both ranges. The comparator determines whether
the addition of each successively weighted bit current causes the
REV. C
–9–
DAC current sum to be greater than or less than the input cur-
rent. If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within
±
1/2 LSB.
CONTROL LOGIC
The AD1674 may be operated in one of two modes, the full-
control mode and the stand-alone mode. The full-control mode
utilizes all the AD1674 control signals and is useful in systems
that address decode multiple devices on a single data bus. The
stand-alone mode is useful in systems with dedicated input ports
available and thus not requiring full bus interface capability.
Table I is a truth table for the AD1674, and Figure 10 illus-
trates the internal logic circuitry.
Table I. AD1674A Truth Table
CE
CS
0
X
1
1
1
1
1
X
1
0
0
0
0
0
R/C
X
X
0
0
1
1
1
12/8 A
0
Operation
X
X
X
X
1
0
0
X
X
0
1
X
0
1
None
None
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs +4 Trailing Zeroes
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