AD5241/AD5242
TIMING DIAGRAMS
t
8
SDA
t
1
t
8
SCL
00926-005
t
9
t
2
t
2
P
S
t
4
t
3
t
6
t
7
S
t
5
P
t
10
Figure 3. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I
2
C bus in the following serial format.
Table 2.
S
0
1
0
1 1 AD1 AD0
Slave Address Byte
R/W
A
A/B
RS
SD O
1
O
2
X
Instruction Byte
X
X
A
D7
D6
D5
D4 D3
Data Byte
D2
D1
D0
A
P
where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/W = Read enable at high and output to SDA. Write enable at low.
A/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as SHDN except inverse logic.
O
1
, O
2
= Output logic pin latched values
D7, D6, D5, D4, D3, D2, D1, D0 = data bits.
1
SCL
SDA
0
1
0
1
1
AD1
AD0
9
1
9
1
9
R/W
A/B
RS
SD
O
1
O
2
X
X
X
ACK BY
AD5241
D7
D6
D5
D4
D3
D2
D1
D0
00926-006
ACK BY
AD5241
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
ACK BY
AD5241
STOP BY
MASTER
Figure 4. Writing to the RDAC Serial Register
1
9
1
9
SCL
SDA
0
1
0
1
1
AD1
AD0
R/W
ACK BY
AD5241
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode
Rev. C | Page 5 of 20
00926-007
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
NO ACK BY
MASTER
STOP BY
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED MASTER
RDAC REGISTER IN WRITE MODE
AD [ ANALOG DEVICES ]
