AD5241/AD5242
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
1
1
W
1
2
B
1
3
V
DD
4
14
O
1
13
NC
O
1 1
A
1 2
W
1 3
B
1 4
16
15
14
A
2
W
2
B
2
TOP VIEW
11
V
SS
(Not to Scale)
10
DGND
SHDN
5
SCL
6
SDA
7
9
8
AD5241
12
O
2
13
O
2
TOP VIEW
V
DD 5
(Not to Scale)
12
V
SS
AD5242
AD1
00926-003
SHDN
6
SCL
7
SDA
8
11
10
9
DGND
00926-004
AD0
AD1
AD0
NC = NO CONNECT
Figure 6. AD5241 Pin Configuration
Figure 7. AD5242 Pin Configuration
Table 4. AD5241 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
A
1
W
1
B
1
V
DD
SHDN
Description
Resistor Terminal A
1
.
Wiper Terminal W
1
.
Resistor Terminal B
1
.
Positive Power Supply, Specified for
Operation from 2.2 V to 5.5 V.
Active low, asynchronous connection of
Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to V
DD
if not used.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
Common Ground.
Negative Power Supply, Specified for
Operation from 0 V to −2.7 V.
Logic Output Terminal O
2
.
No Connect.
Logic Output Terminal O
1
.
Table 5. AD5242 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
O
1
A
1
W
1
B
1
V
DD
SHDN
Description
Logic Output Terminal O
1
.
Resistor Terminal A
1
.
Wiper Terminal W
1
.
Resistor Terminal B
1
.
Positive Power Supply, Specified for
Operation from 2.2 V to 5.5 V.
Active Low, Asynchronous Connection
of Wiper W to Terminal B, and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should
tie to V
DD
, if not used.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
Common Ground.
Negative Power Supply, Specified for
Operation from 0 V to −2.7 V.
Logic Output Terminal O
2
.
Resistor Terminal B
2
.
Wiper Terminal W
2
.
Resistor Terminal A
2
.
6
7
8
SCL
SDA
AD0
7
8
9
SCL
SDA
AD0
9
AD1
10
AD1
10
11
12
13
14
DGND
V
SS
O
2
NC
O
1
11
12
13
14
15
16
DGND
V
SS
O
2
B
2
W
2
A
2
Rev. C | Page 7 of 20
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