Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DV
CC
AV
DD
GND
NC
NC
NC
NC
NC
AD5410/AD5420
GND
DV
CC
FAULT
GND
GND
CLEAR
1
2
3
4
5
6
24
23
AV
DD
NC
NC
NC
BOOST
NC
1
FAULT
2
GND
3
GND
4
CLEAR
5
LATCH
6
SCLK
7
SDIN
8
SDO
9
NC
10
40
39
38
37
36
35
34
NC
33
32
31
30
NC
29
CAP2
28
CAP1
27
BOOST
AD5420
22
21
20
TOP VIEW
(Not to Scale)
19
I
OUT
18
17
16
15
14
13
NC
26
I
OUT
25
NC
24
NC
23
DV
CC
SELECT
22
NC
21
NC
20
AD5420
TOP VIEW
(Not to Scale)
LATCH
7
SCLK
SDIN
8
9
NC
NC
DV
CC
SELECT
REFIN
REFOUT
R
SET
SDO
10
AGND
11
GND
12
11
12
13
14
15
16
17
18
19
R
SET
REFOUT
REFIN
DGND
GND
GND
NC
NC
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
TSSOP Pin No.
1,4,5,12
2
3
LFCSP Pin No.
3,4,15,14,37
39
2
Mnemonic
GND
DV
CC
FAULT
Description
These pins must be connected to 0V.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Fault alert, This pin is asserted low when an open circuit is detected in current mode or
an over temperature is detected. Open drain output, must be connected to a pull-up
resistor.
No Connection.
17,18,21,22, 23
6
7
8
9
10
11
N/A
13
14
15
16
1,10,11,19,
20,21,22,24,25,
30,31,32,33,34,
35,38,40
5
6
7
8
9
12
13
16
17
18
23
NC
CLEAR
LATCH
SCLK
SDIN
SDO
AGND
DGND
R
SET
REFOUT
REFIN
DV
CC
SELECT
I
OUT
BOOST
CAP1
CAP2
AV
DD
AGND
19
20
N/A
N/A
24
Paddle
26
27
28
29
36
Paddle
Active High Input. Asserting this pin will set the current output to the bottom of the
selected range.
Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and Figure 4.
Ground reference pin for analog circuitry.
Ground reference pin for digital circuitry. (AGND and DGND are internally connected in
TSSOP package).
An external, precision, low drift 15kΩ current setting resistor can be connected to this
pin to improve the I
OUT
temperature drift performance. Refer to Features section.
Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for
specified performance.
This pin when connected to GND disables the internal supply and an external supply
must be connected to the DV
CC
pin. Leave this pin unconnected to enable the internal
supply. Refer to features section.
Current output pin.
Optional external transistor connection. Connecting an external transistor will reduce
the power dissipated in the AD5410/AD5420. Refer to the features section.
Connection for optional output filtering capacitor. Refer to Features section.
Connection for optional output filtering capacitor. Refer to Features section.
Positive Analog Supply Pin. Voltage ranges from 10.8V to 40V/60V.
Ground reference for analog circuitry.
Rev. PrE | Page 10 of 30
AGND
NC
AD [ ANALOG DEVICES ]
