AD7682/AD7689
The register can be written to during conversion, during
acquisition, or spanning acquisition/conversion and is updated at
the end of conversion, tCONV (max). There is always a one deep
delay when writing CFG. Note that, at power up, the CFG is
undefined and two dummy conversions are required to update
the register. To preload the CFG with a factory setting, hold
DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This
sets the AD7682/AD7689 for
•
•
•
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
•
No readback of CFG
Table 9 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INCC
INCC
INx
INx
INx
BW
REF
REF
REF
SEQ
SEQ
RB
Table 9. Configuration Register Description
Bit(s)
[13]
Name Description
CFG Configuration update.
0 = Keep current configuration settings.
1 = Overwrite contents of register.
[12:10] INCC
Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended or temperature sensor. Refer to
the Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
0
0
1
1
1
0
1
1
0
1
1
X
0
1
X
0
1
Bipolar differential pairs; INx− referenced to VREF/2 0.1 V.
Bipolar; INx referenced to COM = VREF/2 0.1 V.
Temperature sensor.
Unipolar differential pairs; INx− referenced to GND 0.1 mV.
Unipolar, IN0 to IN7 referenced to COM = GND 0.1 V (GND sense).
Unipolar, IN0 to IN7 referenced to GND.
[9:7]
INx
Input channel selection in binary fashion.
AD7682
AD7689
Bit 9
Bit 8
Bit 7
Channel Bit 9
Bit 8
0
0
…
1
Bit 7
0
1
…
1
Channel
IN0
IN1
0
0
1
1
0
1
0
1
X
X
X
X
IN0
IN1
IN2
IN3
0
0
…
1
IN7
[6]
BW
REF
Select bandwidth for low-pass filter. Refer to the Selectable Low Pass Filter section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughout must be reduced to ¼
also.
1 = Full BW.
[5:3]
Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
Internal reference, REF = 2.5 V output.
Internal reference, REF = 4.096 V output.
External reference, temperature enabled.
External reference, internal buffer, temperature enabled.
External reference, temperature disabled.
External reference, internal buffer, temperature disabled.
[2:1]
SEQ
Channel sequencer. Allows for scanning channels in an IN0 to INx fashion. Refer to the Sequencer section.
Bit 2
Bit 1
Function
0
0
1
1
0
1
0
1
Disable sequencer.
Update configuration during sequence.
Scan IN0 to INx (set in CFG[9:7]), then temperature.
Scan IN0 to INx (set in CFG[9:7]).
0
RB
Read back the CFG register.
0 = Read back current configuration at end of data.
1 = Do not read back contents of configuration.
Rev. 0 | Page 23 of 28
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