AD7682/AD7689
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35. For SPI, the host should use CPHA = CPOL
= 0. Reading/writing spanning conversion is shown, which
covers all three modes detailed in the Digital Interface section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion
irrespective of the state of CNV. CNV must be returned high
before the safe data transfer time, t
DATA
, and then held high
beyond the conversion time, t
CONV
, to avoid generation of the
busy signal indicator.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power down. When the host brings
CNV low after t
CONV
(max), the MSB is enabled on SDO. The
host also must enable the MSB of CFG at this time (if necessary)
AD7682/
AD7689
to begin the CFG update. While CNV is low, both a CFG
update and a data readback take place. The first 14 SCK rising
edges are used to update the CFG, and the first 15 SCK falling
edges clock out the conversion results starting with MSB − 1.
The restriction for both configuring and reading is that they
both occur before the t
DATA
time of the next conversion elapses.
All 14 bits of CFG[13:0] must be written, or they are ignored. In
addition, if the 16-bit conversion result is not read back before
t
DATA
elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16
th
(or 30
th
) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance. If CFG readback is enabled, the CFG associ-
ated with the conversion result
(n
− 1) is read back MSB first
following the LSB of the conversion result. A total of 30 SCK
falling edges is required to return SDO to high impedance if
this is enabled.
DIGITAL HOST
SS
MISO
MOSI
SCK
07353-036
CNV
SDO
DIN
SCK
FOR SPI USE CPHA = 0, CPOL = 0.
Figure 34. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
>
t
CONV
t
CYC
t
CONV
t
CNVH
RETURN CNV HIGH
FOR NO BUSY
t
CONV
t
DATA
t
DATA
RETURN CNV HIGH
FOR NO BUSY
CNV
t
ACQ
ACQUISITION
(n - 1)
CONVERSION (n – 1)
(QUIET
TIME)
UPDATE (n)
CFG/SDO
SCK
14
15
16/
30
1
2
14
15
ACQUISITION (n)
CONVERSION (n)
SEE NOTE
16/
30
(QUIET
TIME)
ACQUISITION
(n + 1)
UPDATE (n + 1)
CFG/SDO
t
CLSCK
CFG
MSB
t
SDIN
CFG
MSB – 1
t
HDIN
CFG
LSB
X
X
SEE NOTE
LSB + 1
DIN
CFG
LSB
X
X
t
EN
END CFG (n)
SDO
LSB + 1
t
EN
LSB
MSB
BEGIN CFG (n + 1)
t
HSDO
t
DSDO
MSB – 1
t
EN
END CFG (n + 1)
LSB
t
DIS
END DATA (n – 2)
t
DIS
BEGIN DATA (n – 1)
t
DIS
END DATA (n – 1)
t
DIS
07353-037
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
Figure 35. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. 0 | Page 24 of 28
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