AD7755
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
DV
DD
Description
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7755.
The supply voltage should be maintained at 5 V
±
5% for specified operation. This pin should be
decoupled with a 10
µF
capacitor in parallel with a ceramic 100 nF capacitor.
High Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current channel).
A logic one on this pin enables the HPF. The associated phase response of this filter has been inter-
nally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be enabled in
power metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7755.
The supply should be maintained at 5 V
±
5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should
be decoupled to AGND with a 10
µF
capacitor in parallel with a ceramic 100 nF capacitor.
No Connect.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with
a maximum differential signal level of
±
470 mV for specified operation. Channel 1 also has a PGA and
the gain selections are outlined in Table I. The maximum signal level at these pins is
±
1 V with respect
to AGND. Both inputs have internal ESD protection circuitry and in addition an overvoltage of
±
6 V
can be sustained on these inputs without risk of permanent damage.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is
±
660 mV for specified operation. The maximum
signal level at these pins is
±
1 V with respect to AGND. Both inputs have internal ESD protection
circuitry and an overvoltage of
±
6 V can also be sustained on these inputs without risk of permanent
damage.
Reset Pin for the AD7755. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7755 internal registers.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V
±
8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may
also be connected at this pin. In either case this pin should be decoupled to AGND with a 1
µF
ceramic capacitor and 100 nF ceramic capacitor.
This provides the ground reference for the analog circuitry in the AD7755, i.e., ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. For
good noise suppression the analog ground plane should only connected to the digital ground plane at
one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency con-
version. This offers the designer greater flexibility when designing the energy meter. See Selecting a
Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for Channel 1, i.e., V1. The possible
gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7755. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and
33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7755. The CLKOUT pin can drive one CMOS load when an external clock is supplied at
CLKIN or by the gate oscillator circuit.
This logic output will go logic high when negative power is detected, i.e., when the phase angle between
the voltage and current signals is greater that 90°. This output is not latched and will be reset when
positive power is once again detected. The output will go high or low at the same time as a pulse is
issued on CF.
2
AC/DC
3
AV
DD
4, 19
5, 6
NC
V1P, V1N
7, 8
V2N, V2P
9
10
RESET
REF
IN/OUT
11
AGND
12
13, 14
SCF
S1, S0
15, 16
17
G1, G0
CLKIN
18
CLKOUT
20
REVP
REV. B
–5–
AD [ ANALOG DEVICES ]
