AD7858/AD7858L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of
CONVST)
before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the
CONVST
signal, the conver-
sion can be initiated in software by writing to the control register.
1.6mA
I
OL
TO
OUTPUT
PIN
+2.1V
C
L
100pF
200 A
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
CONVST
(I/P)
t
2
BUSY (O/P)
t
CONVERT
SYNC
(I/P)
t
3
SCLK (I/P)
1
5
t
9
6
16
t
11
t
10
t
12
DB0
THREE-
STATE
t
4
DOUT (O/P)
THREE-STATE
t
6
DB15
t
6
DB11
t
7
DIN (I/P)
DB15
t
8
DB11
DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
CONVST
(I/P)
t
2
BUSY (O/P)
t
CONVERT
SYNC
(I/P)
t
3
SCLK (I/P)
1
5
t
9
6
16
t
11
t
10
t
12
DB0
THREE-
STATE
t
4
DOUT (O/P)
THREE-STATE
t
6
DB15
t
6
DB11
t
7
DIN (I/P)
DB15
t
8
DB11
DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
REV. B
–5–
AD [ ANALOG DEVICES ]
