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AD8402AR10 参数 Datasheet PDF下载

AD8402AR10图片预览
型号: AD8402AR10
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双/四通道数字电位器 [1-/2-/4-Channel Digital Potentiometers]
分类和应用: 转换器电位器数字电位计电阻器光电二极管PC
文件页数/大小: 20 页 / 497 K
品牌: AD [ ANALOG DEVICES ]
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AD8400/AD8402/AD8403–SPECIFICATIONS
1 k VERSION
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
(V
DD
= +3 V 10% or + 5 V
otherwise noted)
Conditions
10%, V
A
= +V
DD
, V
B
= 0 V, –40 C
T
A
+85 C unless
Min
–5
–4
0.8
Typ
1
–1
±
1.5
1.2
700
53
0.75
Max
+3
+4
1.5
100
2
Units
LSB
LSB
kΩ
ppm/°C
%
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
%
µs
nV/√Hz
dB
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= NC
2
R-INL
R
WB
, V
A
= NC
Resistor Nonlinearity
Nominal Resistance
3
R
T
A
= +25°C, Model: AD840XYY1
V
AB
= V
DD
, Wiper = No Connect
Resistance Tempco
∆R
AB
/∆T
Wiper Resistance
R
W
I
W
= 1 V/R
AB
Nominal Resistance Match
∆R/R
O
CH 1 to 2, V
AB
= V
DD
, T
A
= +25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
INL
Integral Nonlinearity
4
4
Differential Nonlinearity
DNL
V
DD
= +5 V
DNL
V
DD
= +3 V, T
A
= +25°C
Voltage Divider Temperature Coefficent
∆V
W
/∆T
Code = 80
H
Code = FF
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Supply Current
7
Shutdown Wiper Resistance
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
8
Power Dissipation (CMOS)
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
V
A, B, W
C
A, B
C
W
I
DD_SD
R
W_SD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
Range
I
DD
I
DD
P
DISS
PSS
PSS
BW_1K
THD
W
t
S
e
NWB
C
T
8
–6
–4
–5
–20
0
0
±
2
–1.5
–2
25
–12
6
+6
+2
+5
0
10
V
DD
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= +5 V
V
DD
= +5 V
V
DD
= +5 V
V
DD
= +3 V
V
DD
= +3 V
R
L
= 1 kΩ to V
DD
I
OL
= 1.6 mA, V
DD
= +5 V
V
IN
= 0 V or +5 V, V
DD
= +5 V
2.4
75
120
0.01
50
5
100
0.8
2.1
0.6
V
DD
–0.1
0.4
±
1
5
2.7
5.5
0.01
5
0.9
4
27.5
0.0035 0.008
0.05
0.13
5,000
0.015
0.5
3
–65
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= +5.5 V
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V
∆V
DD
= +5 V
±
10%
∆V
DD
= +3 V
±
10%
R = 1 kΩ
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
R
WB
= 500
Ω,
f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
NOTES FOR 1 kΩ VERSION
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
I
W
= 500
µA
for V
DD
= +3 V and I
W
= 4 mA for V
DD
= +5 V for 1 kΩ version.
3
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
DD
versus logic voltage.
9
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
–4–
REV. B