AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(V
Parameter
Symbol
DD
= +5 V, V
SS
= –5 V, All V
IN
x = +3 V, T
A
= –40°C to +85°C, unless otherwise noted.)
Min
8
Typ
Max
Units
Bits
LSB
LSB
LSB
mV
µV/°C
V
kΩ
pF
V
mA
pF
kHz
V/µs
V/µs
%
nV/√Hz
µs
µs
dB
nV-s
14
13
135
0.01
5.25
mA
mA
mW
%/%
V
V
V
µA
pF
Conditions
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution
N
Integral Nonlinearity Error
INL
Differential Nonlinearity
DNL
All Devices Monotonic
Full-Scale Gain Error
G
FSE
PR
= 0, Sets D = 80
H
Output Offset
V
BZE
Output Offset Drift
TCV
BZ
PR
= 0, Sets D = 80
H
VOLTAGE INPUTS—Applies to All Inputs V
IN
x
IVR
Input Voltage Range
1
Input Resistance
R
IN
Input Capacitance
C
IN
DAC OUTPUTS—Applies to All Outputs V
OUT
x
OVR
Voltage Range
1
Output Current
I
OUT
Capacitive Load
C
L
R
L
= 10 kΩ
∆V
OUT
< 1.5 LSB
No Oscillation
±
0.2
±
0.4
2
5
5
±
4
19
9
±
4
500
±
1
±
1
25
±
3
12
±
3
±
3
DYNAMIC PERFORMANCE—Applies to All DACs
GBW
V
IN
x =
±
3 V
P
, R
L
= 2 kΩ, C
L
= 10 pF
Full Power Gain Bandwidth
1
Slew Rate
Measured 10% to 90%
Positive
SR+
∆V
OUT
x = +5.5 V
Negative
SR–
∆V
OUT
x = –5.5 V
Total Harmonic Distortion
THD
V
IN
x = 4 V p-p, D = FF
H
, f = 1 kHz,
f
LPF
= 80 kHz, R
L
= 1 kΩ
f = 1kHz, V
IN
= 0 V
Spot Noise Voltage
e
N
±
1 LSB Error Band, D = 00
H
to FF
H
Output Settling Time
t
S
D = FF
H
to 00
H
Measured Between Adjacent
Channel-to-Channel Crosstalk
C
T
Channels, f = 100 kHz
Digital Feedthrough
Q
V
IN
x = 0 V, D = 0 to 255
10
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Dissipation
2
Power Supply Rejection
Power Supply Range
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
DIGITAL OUTPUT
Logic High
Logic Low
TIMING SPECIFICATIONS
1
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load Edge to Next Clock Edge
I
DD
I
SS
P
DISS
PSRR
PSR
V
IH
V
IL
I
L
C
IL
PR
= 0 V
PR
= 0 V
PR
= 0 V,
∆V
DD
=
±
5%
V
DD
, |V
SS
|
10
0.5
1.0
50
1.0
1.8
0.01
78
2.9
5.4
72
5
10
9
95
0.0001
5.00
4.75
2.4
0.8
±
10
7
Offset Binary
I
OH
= –0.4 mA
I
OL
= 1.6 mA
3.5
0.4
60
40
20
80
70
50
30
60
V
OH
V
OL
t
CH
, t
CL
t
DS
t
DH
t
PD
t
LD
t
PR
t
CKLD
t
LDCK
V
V
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Guaranteed by design, not subject to production test.
2
Calculated limit = 5 V
×
(I
DD
+ I
SS
).
Specifications subject to change without notice.
–2–
REV. 0
AD [ ANALOG DEVICES ]
