AD9850
Parameter
CMOS LOGIC INPUTS (Including CLKIN)
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
POWER SUPPLY (A
OUT
= 1/3 CLKIN)
+V
S
Current @:
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
P
DISS
@:
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
P
DISS
Power-Down Mode
+5 V Supply
+3.3 V Supply
NOTES
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
Temp
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Test Level
I
I
I
I
I
V
AD9850BRS
Min Typ Max
3.5
3.0
0.4
12
12
3
Units
V
V
V
µA
µA
pF
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
VI
VI
V
V
30
47
44
76
100
155
220
380
30
10
48
60
64
96
160
200
320
480
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
TIMING CHARACTERISTICS*
(V = +5 V
S
5% except as noted, R
SET
= 3.9 k )
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
AD9850BRS
Min
Typ Max
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
Parameter
t
DS
t
DH
t
WH
t
WL
t
WD
t
CD
t
FH
t
FL
t
CF
t
FD
t
RH
t
RL
t
RS
t
OL
t
RR
(Data Setup Time)
(Data Hold Time)
(W_CLK min. Pulsewidth High)
(W_CLK min. Pulsewidth Low)
(W_CLK Delay After FQ_UD)
(CLKIN Delay After FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Min. Delay After W_CLK)
(CLKIN Delay After RESET Rising Edge)
(RESET Falling Edge After CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
NOTES
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
REV. E
–3–
AD [ ANALOG DEVICES ]
