AD9850
Table I. Lead Function Descriptions
Pin
No.
4–1,
28–25
5, 24
6, 23
7
8
9
10, 19
11, 18
12
Mnemonic
D0–D7
DGND
DVDD
W_CLK
FQ_UD
CLKIN
AGND
AVDD
R
SET
Function
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.
Digital Ground. These are the ground return leads for the digital circuitry.
Supply Voltage Leads for digital circuitry.
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)
loaded in the data input register, it then resets the pointer to Word 0.
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
Supply Voltage for the analog circuitry (DAC and comparator).
This is the DAC’s external R
SET
connection. This resistor value sets the DAC full-scale output current. For
normal applications (F
S
I
OUT
= 10
mA),
the value for R
SET
is 3.9 kΩ connected to ground. The R
SET
/I
OUT
relationship is:
I
OUT
= 32 (1.248 V/R
SET
).
Output Complement. This is the comparator’s complement output.
Output True. This is the comparator’s true output.
Inverting Voltage Input. This is the comparator’s negative input.
Noninverting Voltage Input. This is the comparator’s positive input.
13
14
15
16
17
20
21
22
QOUTB
QOUT
VINN
VINP
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a “no connect” for optimum performance.
IOUTB
IOUT
RESET
The Complementary Analog Output of the DAC.
Analog Current Output of the DAC.
Reset. This is the master reset function; when set high it clears all registers (except the input register) and
the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.
PIN CONFIGURATIONS
D3
D2
D1
LSB D0
DGND
DVDD
W CLK
FQ UD
CLKIN
1
2
3
4
5
6
7
28
D4
27
D5
26
D6
25
D7 MSB/SERIAL LOAD
24
DGND
23
DVDD
22
RESET
TOP VIEW
8
(Not to Scale) 21
IOUT
AD9850
9
20
IOUTB
19
AGND
18
AVDD
17
DACBL (NC)
16
VINP
15
VINN
AGND 10
AVDD 11
R
SET
12
QOUTB 13
QOUT 14
NC = NO CONNECT
REV. E
–5–
AD [ ANALOG DEVICES ]
