AD5570
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
V
DD
= +12 V ± 5%, V
SS
=
−12
V ± 5% or V
DD
= +15 V ± 10%, V
SS
=
−15
V ± 10%; V
REF
= 5 V; REFGND = GND = 0 V; R
L
= 5 kΩ,
and C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
141
Limit at T
MIN
, T
MAX
2
500
200
200
10
35
0
45
45
0
50
200
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
Data delay on SDO
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2.
SDO; R
PULLUP
= 5 kΩ, C
L
= 15 pF.
1
With C
L
= 0 pF, t
15
= 100 ns.
t
1
SCLK
t
8
SYNC
t
4
t
3
t
2
t
7
t
10
LDAC
1
t
9
LDAC
2
t
6
t
5
SDIN
DB15 (N)
DB0 (N)
DB15
(N+1)
DB0
(N+1)
t
14
SDO
DB15 (N)
DB0 (N)
DB15
(N+1)
03760-0-003
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE
2. SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
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