ADCMP551/ADCMP552/ADCMP553
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
V
CCO
1
2
20
19
18
17
16
15
14
13
12
11
CCO
QA
QB
QB
V
1
2
3
4
5
6
7
8
16 QB
15 QB
QA
QA
QA
3
ADCMP552
TOP VIEW
(Not to Scale)
V
4
CCO
CCO
14
V
CCO
LEA
LEA
LEB
V
5
CCO
ADCMP551
TOP VIEW
(Not to Scale)
13 LEB
12 LEB
11 AGND
10 –INB
LEB
LEA
LEA
6
1
2
3
4
8
7
6
5
AGND
LEA
LEA
V
AGND
–INB
+INB
HYSB
7
CCI
ADCMP553
TOP VIEW
(Not to Scale)
V
CC
–INA
+INA
V
8
CCI
QA
QA
+INA
–INA
–INA
+INA
9
+INB
9
HYSA
10
Figure 2. ADCMP551 16-Lead QSOP
Pin Configuration
Figure 3. ADCMP552 20-Lead QSOP
Pin Configuration
Figure 4. ADCMP553 8-Lead MSOP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP551 ADCMP552 ADCMP553 Mnemonic Function
3, 14
1
1, 4, 17, 20
2
VCCO
QA
Logic Supply Terminal.
6
5
2
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
2
4
3
5
QA
QA
One of Two Complementary Outputs for Channel A. is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
LEA
LEA
prior to the comparator’s being placed in the latch mode.
conjunction with LEA.
must be driven in
5
6
1
LEA
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
LEA
conjunction with
.
6
7
7
8
VCCI
−INA
Input Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The
inverting A input must be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The
noninverting A input must be driven in conjunction with the inverting A input.
4
3
8
9
+INA
10
11
12
HYSA
HYSB
+INB
Programmable Hysteresis.
Programmable Hysteresis.
Noninverting Analog Input of the Differential Input Stage for Channel B. The
noninverting B input must be driven in conjunction with the inverting B input.
9
10
11
13
14
−INB
Inverting Analog Input of the Differential Input Stage for Channel B. The
inverting B input must be driven in conjunction with the noninverting B input.
Analog Ground.
8
AGND
Rev. A | Page 6 of 16
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