ADuC7019/20/21/22/24/25/26/27/28/29
Parameter
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
START-UP TIME
At Power-On
From Pause/Nap Mode
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS
Power Supply Voltage Range
AV
DD
to AGND and IOV
DD
to IOGND
Analog Power Supply Currents
AV
DD
Current
DACV
DD
Current
Digital Power Supply Current
IOV
DD
Current in Normal Mode
Min
Typ
326
41.78
0.05
0.05
130
24
3.06
1.58
1.7
12
2.5
44
41.78
Max
Unit
kHz
MHz
MHz
MHz
ms
ns
µs
ms
ms
ns
ns
Test Conditions/Comments
CD
= 7
CD
= 0
T
A
= 85°C
T
A
= 125°C
Core clock = 41.78 MHz
CD
= 0
CD
= 7
Data Sheet
From input pin to output pin
2.7
200
400
3
3.6
V
µA
µA
µA
ADC in idle mode; all parts except ADuC7019
ADC in idle mode; ADuC7019 only
25
IOV
DD
Current in Pause Mode
IOV
DD
Current in Sleep Mode
Additional Power Supply Currents
ADC
DAC
ESD TESTS
HBM Passed Up To
FCIDM Passed Up To
1
2
7
11
40
25
250
600
2
0.7
700
10
15
45
30
400
1000
mA
mA
mA
mA
µA
µA
mA
mA
µA
Code executing from Flash/EE
CD
= 7
CD
= 3
CD
= 0 (41.78 MHz clock)
CD
= 0 (41.78 MHz clock)
T
A
= 85°C
T
A
= 125°C
@ 1 MSPS
@ 62.5 kSPS
per DAC
2.5 V reference, T
A
= 25°C
4
0.5
kV
kV
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external
op amp as an input buffer stage as shown in Figure 59. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (V
CM
) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V
REF
.
9
Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11
Test carried out with a maximum of eight I/Os set to a low output level.
12
See the POWCON register.
13
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14
IOV
DD
power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15
On the ADuC7019/20/21/22, this current must be added to the AV
DD
current.
Rev. F | Page 12 of 104
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