Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width1
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
SCLK high pulse width1
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge2
Data input hold time after SCLK edge2
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
25
75
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6 TO 1
LSB
MSB IN
BITS 6 TO 1
LSB IN
tDSU
tDHD
Figure 16. SPI Master Mode Timing (Phase Mode = 0)
Rev. F | Page 17 of 104
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