ATF-531P8 Electrical Specifications
T
A
= 25°C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified.
Symbol
Vgs
Vth
Idss
Gm
Parameter and Test Condition
Operational Gate Voltage
Threshold Voltage
Saturated Drain Current
Transconductance
Vds = 4V, Ids = 135 mA
Vds = 4V, Ids = 8 mA
Vds = 4V, Vgs = 0V
Vds = 4.5V, Gm =
∆Idss/∆Vgs;
?Vgs = Vgs1 - Vgs2
Vgs1 = 0.6V, Vgs2 = 0.55V
Vds = 0V, Vgs = -4V
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
Offset BW = 5 MHz
Offset BW = 10 MHz
Units
V
V
µA
mmho
Min.
—
—
—
—
Typ.
0.68
0.3
3.7
650
Max.
—
—
—
—
Igss
NF
G
OIP3
P1dB
PAE
ACLR
Gate Leakage Current
Noise Figure
[1]
Gain
[1]
Output 3
rd
Order
Intercept Point
[1,2]
Output 1dB
Compressed
[1]
Power Added Efficiency
Adjacent Channel Leakage
Power Ratio
[1,3]
µA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
%
%
dBc
dBc
-10
—
—
18.5
—
35.5
—
—
—
—
—
—
—
-0.34
0.6
0.6
20
25
38
37
24.5
23
57
45
-68
-64
—
1
—
21.5
—
—
—
—
—
—
—
—
—
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. F1 = 2.00 GHz, F2 = 2.01 GHz and Pin = -10 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag
= 0.66
Γ_ang
= -165°
(1.8 dB loss)
DUT
Output
Matching Circuit
Γ_mag
= 0.09
Γ_ang
= 118°
(1.1 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a
trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
3
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