2
The design of the HDMP-0421
allows for placement of the CDR
at one of two locations with
respect to a hard disk slot. For
example, if the BYPASS[0]– pin
is HIGH and hard disk slot A is
connected to PBC cell 1, the CDR
function will be performed before
entering the hard disk at slot A
(Figure 4). To achieve a CDR
function after slot A, the
BYPASS[1]– pin must be HIGH
and hard disk slot A must be
connected to PBC cell 0
(Figure 5). Table 2 shows both
possible connections. In both
cases, a Signal Detect (SD) pin
shows the status of the signal at
the incoming cable. The
recommended method of setting
the BYPASS[i]– pins HIGH is to
drive them with a high-
impedence signal. Internal pull-
up resistors will force the
BYPASS[I]– pins to V
CC
.
FM_NODE[1]
FM_NODE[0]
TO_NODE[1]
LOSDET
TO_NODE[0]
BYPASS[1]–
1
0
SD[1]
1
0
BYPASS[0]–
CDR
CEXT
IOSDET
REFCLK
SD[0]
Figure 1. Block Diagram of HDMP-0421.
(1) FM_NODE[0]
(2) FM_NODE[4]
(1) TO_NODE[0]
(2) TO_NODE[0]
t
delav1.2
Figure 2. Timing Waveforms.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
