4
Table 3. Pinout
Pin Name
TO_NODE[0]+
TO_NODE[0]–
FM_NODE[1]+
FM_NODE[1]–
TO_NODE[1]+
TO_NODE[1]–
FM_NODE[0]+
FM_NODE[0]–
BYPASS[1]–
BYPASS[0]–
REFCLK
CPLL1
CPLL0
SD[1]
SD[0]
Pin
20
21
02
01
05
04
23
24
08
17
14
12
13
09
16
Pin Type
Pin Description
O-PECL In CDR at entry configuration, this pin is the Serial Output
(TO_LOOP+). In other configurations, this pin is wired to the hard disk.
O-PECL In CDR at entry configuration, this pin is the Serial Output
(TO_LOOP–). In other configurations, this pin is wired to the hard disk.
I-PECL Input from Transceiver IC to Cell 1.
I-PECL Input from Transceiver IC to Cell 1.
O-PECL Output to Transceiver IC from Cell 1.
O-PECL Output to Transceiver IC from Cell 1.
I-PECL In CDR at entry configuration, this pin is the Serial Input
(FM_LOOP+). In other configurations, this pin is wired to the hard disk.
I-PECL In CDR at entry configuration, this pin is the Serial Input
(FM_LOOP–). In other configurations, this pin is wired to the hard disk.
I-LVTTL Bypass pin for cell 1. In CDR at exit configuration, float to HIGH else
ground connect through a 1 KΩ resistor.
I-LVTTL Bypass pin for cell 0. In CDR at exit configuration, float to HIGH else
ground connect through a 1 KΩ resistor.
I-LVTTL Reference Clock Input for Clock and Data Recovery (CDR) circuit.
C
PLL cap pin. Connected to pin 13 with a 0.1 microFarad capacitor.
C
PLL cap pin. Connected to pin 12 with a 0.1 microFarad capacitor.
O-LVTTL Signal Detect via envelope detect method. In CDR at entry and at exit
cases, detects signal on incoming cable respectively. Active High when
signal is detected.
If (FM_NODE[0]+ –FM_NODE[0]–) >= 400 mV peak-to-peak, SD = 1
If 400 mV >= (FM_NODE[0]+ –FM_NODE[0]–) >= 100 mV,
SD = unpredictable
If 100 mV >= (FM_NODE[0]+ –FM_NODE[0]–), SD = 0
S
6, 7, 11, 18, 19 Ground pins.
S
Analog Power Supply pin.
S
Cell 1 High Speed Output Pins Power Supply.
S
Cell 0 High Speed Output Pins Power Supply.
S
Logic Power Supply pins.
GND
V
CC
A
V
CC
HS
V
CC
15
03
22
10
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