Page 8
Device Configuration
shows the basic configuration interface connections between a configuration
device chain and the Altera FPGA.
Figure 3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices
V
CC
V
CC
V
CC
(3)
(2)
(3)
FPGA
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL
nCEO
nCE
N.C.
Master
Configuration
Device
DCLK
DATA
OE
(3)
nCS
(3)
nCASC
nINIT_CONF
(2)
Slave
Configuration
Device
DCLK
DATA
nCS
OE
n
nCASC
N.C.
GND
Notes to
(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.
(2) The
nINIT_CONF
pin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the
nINIT_CONF/nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its functionality is not used.
If the
nINIT_CONF
pin is not used or unavailable,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
(3) EPC2 devices have internal programmable pull-up resistors on
OE
and
nCS
pins. If internal pull-up resistors are used, do not use external pull-up
resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check
the
Disable
nCS
and OE
pull-ups
on
configuration
device
option when you generate programming files.
When the first device in a configuration device chain is powered-up or reset, its
nCS
pin is driven low because it is connected to the
CONF_DONE
pin of the FPGA. Because
both
OE
and
nCS
pins are low, the first device in the chain recognizes it as the master
device and controls configuration. Since the slave devices’
nCS
pin is fed by the
previous devices’
nCASC
pin, its
nCS
pin is high after power-up and reset. In the slave
configuration devices, the
DATA
output is tri-stated and
DCLK
is an input. During
configuration, the master device supplies the clock through
DCLK
to the FPGA and to
any slave configuration devices. The EPC1 or EPC2 master device also provides the
first stream of data to the FPGA during multi-device configuration. After the EPC1 or
EPC2 master device finishes sending configuration data, it tri-states its
DATA
pin to
avoid contention with other configuration devices. The EPC1 or EPC2 master device
also drives its
nCASC
pin low, which pulls the
nCS
pin of the next device low. This
action signals the EPC1 or EPC2 slave device to start sending configuration data to the
FPGAs.
The EPC1 or EPC2 master device clocks all slave configuration devices until
configuration is complete. When all configuration data is transferred and the
nCS
pin
on the EPC1 or EPC2 master device is driven high by the FPGA’s
CONF_DONE
pin, the
EPC1 or EPC2 master device then goes into zero-power (idle) state. The EPC2 master
device drives
DATA
high and
DCLK
low, while the EPC1 and EPC1441 device tri-state
DATA
and drive
DCLK
low.
If the
nCS
pin on the EPC1 or EPC2 master device is driven high before all
configuration data is transferred, the EPC1 or EPC2 master device drives its
OE
signal
low, which in turn drives the FPGA’s
nSTATUS
pin low, indicating a configuration
error. Additionally, if the configuration device generates its data and detects that the
CONF_DONE
pin has not gone high, it recognizes that the FPGA has not configured
successfully. EPC1 and EPC2 devices wait for 16
DCLK
cycles after the last
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
