AD6311
1/8- to 1/16 Duty VFD Controller/Driver
(2) Key Scanning and Display Timing
T
DISP
≅
500
μ
s
Key scan data
DIG2
DIG3
DIGn
DIG1
SEG Output
DIG1
Grid1
Grid2
1/16
T
DISP
Gird3
Gridn
1 frame = T
DISP
×
(n+1)
One cycle of key scanning consists of two frames, and data of 12× 4 matrices is stored in RAM.
AC characteristic waveform
fosc
OSC
50%
PW
STB
STB
PW
CLK
PW
CLK
t
CLK-STB
CLK
t
SETUP
D
IN
t
HOLD
tPZL
D
OUT
t
TZH
tPLZ
Sn/Gn
90%
10%
t
THZ
Anachip Corp.
www.anachip.com.tw
9/11
Rev. A5 Dec 29, 2003