different settling times. This may result in offset error, gain
error, and linearity error which change with both tempera-
ture and input voltage. If the impedance cannot be matched,
the errors can be lessened by giving the ADS8321 additional
acquisition time.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8321 charges the inter-
nal capacitor array during the sample period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to 16-bit settling level
within 4.5 clock cycles. When the converter goes into the
hold mode or while it is in the power-down mode, the input
impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +In input should always remain within the
range of GND – 300mV to V
CC
+ 300mW. The –In input
should always remain within the range of GND – 300mV to
4V. Outside of these ranges, the converter’s linearity may
not meet specifications.
NOISE
The noise floor of the ADS8321 itself is extremely low, as
can be seen from Figures 4 and 5, and is much lower than
competing A/D converters. It was tested by applying a low
noise DC input and a 2.5V reference to the ADS8321 and
initiating 5,000 conversions. The digital output of the A/D
converter will vary in output code due to the internal noise
of the ADS8321. This is true for all 16-bit SAR-type A/D
converters. Using a histogram to plot the output codes, the
distribution should appear bell-shaped with the peak of the
bell curve representing the nominal code for the input value.
The
±1σ, ±2σ,
and
±3σ
distributions will represent the
68.3%, 95.5%, and 99.7%, respectively, of all codes. The
transition noise can be calculated by dividing the number of
codes measured by 6 and this will yield the
±3σ
distribution
or 99.7% of all codes. Statistically, up to 3 codes could fall
outside the distribution when executing 1000 conversions.
The ADS8321, with five output codes for the
±3σ
distribu-
tion, will yield a
±0.8LSB
transition noise. Remember, to
achieve this low noise performance, the peak-to-peak noise
of the input signal and reference must be < 50µV.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8321 will operate with a reference in the range of
500mV to 2.5V. There are several important implications of
this. As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the Least Significant Bit (LSB) size and is
equal to 2 • V
REF
divided by 65,535. This means that any
offset or gain error inherent in the A/D converter will appear
to increase, in terms of LSB size, as the reference voltage is
reduced.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a +2.5V reference, the
internal noise of the converter typically contributes only 5
LSB peak-to-peak of potential error to the output code. When
the external reference is 500mV, the potential error contribu-
tion from the internal noise will be 10 times larger—15 LSBs.
The errors due to the internal noise are gaussian in nature and
can be reduced by averaging consecutive conversion results.
For more information regarding noise, consult the typical
performance curve “Noise vs Reference Voltage.” Note that
the Effective Number of Bits (ENOB) figure is calculated
based on the converter’s signal-to-(noise + distortion) ratio
with a 1kHz, 0dB input signal. SINAD is related to ENOB
as follows:
SINAD = 6.02 • ENOB + 1.76
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
1639
1260
981
0
12
192
13
14
15
Code
16
24
17
0
18
FIGURE 4. Histogram of 5,000 Conversions of a DC Input
at the Code Transition.
2318
836
696
244
0
12
13
14
15
Code
16
2
17
0
18
FIGURE 5. Histogram of 5,000 Conversions of a DC Input
at the Code Center.
®
ADS8321
8
BURR-BROWN [ BURR-BROWN CORPORATION ]
