AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to
±0.25
LSBs. Averaging should only be used for input signals with
frequencies near DC.
For AC signals, a digital filter can be used to low pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
SYMBOL
t
SMPL
t
CONV
t
CYC
t
CSD
t
SUCS
t
hDO
t
dDO
t
dis
t
en
DESCRIPTION
Analog Input Sample Time
Conversion Time
Throughput Rate
CS Falling to
DCLOCK LOW
CS Falling to
DCLOCK Rising
DCLOCK Falling to
Current D
OUT
Not Valid
DCLOCK Falling to Next
D
OUT
Valid
CS Rising to D
OUT
Tri-State
DCLOCK Falling to D
OUT
Enabled
D
OUT
Fall Time
D
OUT
Rise Time
MIN
4.5
TYP
MAX
5.0
UNITS
Clk Cycles
Clk Cycles
16
100
0
kHz
ns
20
ns
5
15
30
70
20
5
7
50
100
50
25
25
ns
ns
ns
ns
ns
ns
DIGITAL INTERFACE
SIGNAL LEVELS
The digital inputs of the ADS8321 can accommodate logic
levels up to 5.5V regardless of the value of V
CC
.
The CMOS digital output (D
OUT
) will swing 0V to V
CC
. If
V
CC
is 3V and this output is connected to a 5V CMOS logic
input, then that IC may require more supply current than
normal and may have a slightly longer propagation delay.
SERIAL INTERFACE
The ADS8321 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 6 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for D
OUT
is acceptable, the
system can use the falling edge of DCLOCK to capture each
bit.
t
f
t
r
TABLE I. Timing Specifications (V
CC
= 5V) –40°C to +85°C.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, D
OUT
will output the conversion result, most signifi-
cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B15) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
Complete Cycle
CS/SHDN
t
SUCS
Sample
DCLOCK
t
CSD
D
OUT
Hi-Z
0
t
SMPL
B15 B14 B13 B12 B11 B10 B9 B8
(MSB)
t
CONV
B7
B6
B5 B4 B3
B2
B1
B0
(LSB)
Use positive clock edge for data transfer
Hi-Z
Conversion
Power Down
NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
FIGURE 6. ADS8321 Basic Timing Diagrams.
®
9
ADS8321
BURR-BROWN [ BURR-BROWN CORPORATION ]
