SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1741 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modu-
lators. The system clock is applied at the SCK input (pin 16).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator from Texas Instruments is an excellent choice
for providing the PCM1741 system clock.
POWER-ON RESET FUNCTIONS
The PCM1741 includes a power-on reset function, as shown in
Figure 2. With the system clock active, and V
DD
> 2.0V (typical
1.6V to 2.4V), the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time V
DD
> 2.0V. After the initialization period, the PCM1741
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level, or V
CC
/2. After
the reset period, the internal register is initialized in the next
1/f
S
period and, if SCK, BCK, and LRCK are provided
continuously, the PCM1741 provides proper analog output
with unit group delay against the input data.
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
SAMPLING
FREQUENCY
8kHz
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
256f
S
2.0480
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
384f
S
3.0720
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
512f
S
4.0960
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
768f
S
6.1440
12.2880
24.5760
33.8688
36.8640
See Note (1)
See Note (1)
NOTE: (1) The 768f
S
system clock rate is not supported for f
S
> 64kHz.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
t
SCKH
“H”
System Clock
“L”
t
SCKL
System clock pulse
cycle time
(1)
0.8V
2.0V
System Clock Pulse Width HIGH t
SCKH
: 7ns (min)
System Clock Pulse Width LOW t
SCKL
: 7ns (min)
NOTE: (1) 1/256f
S
, 1/384f
S
, 1/512f
S
, and 1/768f
S
.
FIGURE 1. System Clock Input Timing.
2.4V
V
DD
2.0V
1.6V
0V
Reset
Internal Reset
Don't Care
System Clock
1024 System Clocks
Reset Removal
FIGURE 2. Power-On Reset Timing.
8
PCM1741
SBAS175
BURR-BROWN [ BURR-BROWN CORPORATION ]
