BL1102series
Known from the above block diagram, it mainly made up of system clock generator, keyboard interface,
data code, random storing, read/write counter, address lock and storing, system control logic, pulse
generator, data/mode converter and double tone generator and other circuits.
。
Pin Description
Symbol
Row/colum
n input
X T,X T
T/P MUTE
22 Pin
1-4,18-
22
6,7
8
24 Pin
1-4,20-
24
6,7
8
I/0
O
I/0
I
Function
A valid key entry is defined by a single row being
Connected to a single column
Oscillation I/O
The T/P MUTE is a conventional CMOS N-channel
open drain output. When dialing and flash, the
output is
and will turn down the talking network.
Dialing mode selection.. When pin is connected to
VSS, it is double tone multi-frequency mode when it is
connected to VDD; it is pulse mode (10ppS).
The pin is the hook switch input HKS =1, on HOOK
state, chip in sleeping mode, no operation. HKS =0, on
HOOK state，enable chip on normal operation.
Break/make ratio, pin selection.
B/M=1, ratio is 60/40;
B/M=0, ratio is 66/33.
Power and power ground input
Inverter output. Dialing under double tone mode,
pin is high voltage； dialing under pulse mode, the
if
pin is low voltage.
Hands-free control details can be seen in table2.
Key tone signal output. The frequency is1.2KHz.
Once the pin is locked, dialing starting with
"0" or "9" and all the key input afterwards will
become invalid. It will recover the original state
after on hook
LOCK Pin
Function
VDD
“0”和“9”dialing lim it
Floating
Normal
VSS
“0”dialing lim it
Not available
The DP/C5 is a conventional CMOS N-channel
open drain output. Under tone state. Output will
keep high; Under pulse state, output dialing pulse.
Double tone multifrequency signal output
MODE
14
16
I
HKS
9
9
I
B/M
VDD, VSS
X MUTE
HFI, HFO
KT
16
1 7, 5
13
--
12
18
19, 5
15
12，13
14
I
I
O
I/O
O
LOCK
15
(BL1102L)
17
(BL1102AL)
I
NC
DP / C5
15
(BL1102)
10
17
(BL1102A)
10
I
O
DTMF
11
11
O
http://www.belling.com.cn
-2-
8/22/2006
Wrote by 2006
Total
9 Pages
BELLING [ SHANGHAI BELLING CO., LTD. ]
