BL7442LV Low voltage
Intelligent 2K bits EEPROM
Command
1
CLK
2
3
4
23
24
IFD sets I/O to State L
I/O
START
From IFD
CLK
td1
tBUF
I/O
tF
td7
STOP
From IFD
tR
td5
td8
td3
tL
Figure 4 Command Mode
After the reception of a command there are two possible modes:
--Outgoing data mode for reading
--Processing mode for writing and erasing
(3) Outgoing Data Mode
In this mode the IC sends data to the IFD. Figure 5 shows the timing diagram. The first bit becomes
valid on I/O after the first falling edge on CLK. After the last data bit an additional clock pulse is necessary in
order to set I/O to state H and to prepare the IC for a new command entry. During this mode any start and
stop condition is discarded.
Command
CLK
1
2
3
4
n-1
n
IC sets I/O to State H
I/O
1
Start of Outgoing Data
2
3
n-1
n
Figure 5 Outgoing Data Mode
(4) Processing Mode
In this mode the IC processes internally. Figure 6 shows the timing diagram. The IC has to be clocked
continuously until I/O which was switched to state L after the first falling edge of CLK is set to state H. Any
start and stop condition id discarded during this mode.
CLK
I/O
1
2
3
n-1
n
Start of
Processing
td2
td2
End of
Processing
Figure 6 Processing Mode
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Total
10 Pages
8/16/2006
BELLING [ SHANGHAI BELLING CO., LTD. ]
