BL7442LV Low voltage
Intelligent 2K bits EEPROM
Figure 8 Verification Procedure
Reset Modes
(1) Power-on-Reset
After connecting the operating voltage to VCC ,I/O is state H. By all means, a read access to an
address or an Answer-to-Reset must be carried out before data can be altered.
(2) Break
If RST is set to high during CLK in state L any operation is aborted and I/O is switched to state H.
Minimum duration of Tres=5us is necessary to trigger a defined valid reset(figure 9).After Break
the chip is ready for further operations.
RST
t
RCS
t
d9
CLK
I/O
Figure 9 Break
Failures
Behavior in case of failures:
In case of one of the following failures, the chip sets the I/O to state H after 8 clock pulses at the
latest.
Possible failures:
--Comparison unsuccessful
--Wrong command
--Wrong number of command clock pulses
--Write/erase access to already protected bytes
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8/16/2006
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