2FAH-C20R Series - Integrated Passive & Active Device using CSP
Mechanical Characteristics
This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5mm. The dimensions for the CSP packaged device are shown in Fig. 2 below.
858
±
40
(33.78
±
1.57)
248.5
±
45
(9.78
±
1.78)
BUMP A1/PIN 1
INDICATOR
BOURNS
LOGO
A1
B1
C1
D1
A2
B2
C2
D2
500
(19.69)
A3
B3
300
DIA.
(11.81)
C3
D3
2597
±
45
(102.24
±
1.78)
A4
B4
C4
D4
500
(19.69)
A5
B5
C5
D5
225
±
20
(8.86
±
0.79)
348.5
±
45
(13.72
±
1.78)
248.5
±
45
(9.78
±
1.78)
45
±
45
(1.78
±
1.78)
45
±
45
(1.78
±
1.78)
DIMENSIONS =
MICRONS
(MILS)
1997
±
45
(78.62
±
1.78)
Fig. 2 – Device Mechanical Drawing
Reliability
Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP
packaging.
“Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2FAH-C20R and is thus deemed a
worse case for Thermal Cycle testing.
“Silicon level” reliability performance will be assured by similarity to other Integrated Passive and Active Devices using CSP product
from Bourns.
Individual Channel Schematic
This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical
parameters of primary interest are (a) DC Resistance and (b) ESD performance. In terms of DC parameters it should be noted that all
resistor values have a tolerance of ±10 %. This schematic consists of a series 100ohm resistance and Back to Back Zener 6.5 Volt
diodes for ESD protection.
IN
100Ω
OUT
±6.5V
Key Design Parameters
DC Channel Resistance: 100
Ω
±10 %
DC Channel Capacitance: 12.5 pF Maximum
V
BR
: 6 V Min, 8 V Max @ I
BR
= 1 mA.
I
R
: 1 uA Max @ V
R
=3 V.
Fig. 3 – Channel Schematic
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
BOURNS [ BOURNS ELECTRONIC SOLUTIONS ]
