2FAH-C20R Series - Integrated Passive & Active Device using CSP
Block Diagram
Figure 4 contains a block diagram of the CSP device. This diagram includes the pin
names and basic electrical connections associated with each channel.
Marking
The device will be laser marked on the
backside according to the following Fig.
5 scheme below. Position A1, on the
Bump Grid is located at the top left of the
die when the die is orientated so that the
mark is read in the normal fashion.
PIN A1
LOCATION
IN1
100Ω
±6.5V
OUT1
1 2 3 4 5
FAH
Lotcode
A
IN2
100Ω
±6.5V
OUT2
B
C
OUT3
IN3
100Ω
±6.5V
D
Fig. 5 – Backside Laser Mark
IN4
100Ω
±6.5V
OUT4
PCB Design and SMT Processing
OUT5
100Ω
IN5
±6.5V
Please consult Bourns’
Thin Film on
Silicon using CSP
Users Guide
Application Note for notes on PCB
design and SMT processing.
How to Order
IN6
100Ω
OUT6
2 FAH - C20R ____
±6.5V
Thinfilm
Model
Chipscale
No. of Solder Bumps
Packaging Option
R = Tape and Reel
Packaged 3000 pcs. / 7 ” reel
Terminations
LF = Sn/Ag/Cu (lead free)
Blank = Sn/Pb
IN7
100Ω
±6.5V
OUT7
GROUND
GROUND
Fig. 4 – Device Block Diagram
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
BOURNS [ BOURNS ELECTRONIC SOLUTIONS ]
