BS616LV2019
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
(3)
I
CCDR
O
O
PARAMETER
V
CC
for Data Retention
TEST CONDITIONS
CE≧V
CC
-0.2V or CE2
(4)
≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V or CE2
(4)
≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
Data Retention Current
Chip Deselect to Data
Retention Time
--
0.1
1.0
uA
t
CDR
t
R
0
See Retention Waveform
t
RC (2)
--
--
ns
Operation Recovery Time
--
--
ns
1. V
CC
=1.5V, T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCDR(Max.)
is 0.7uA at T
A
=70
O
C.
4. 48B BGA ignore CE2 condition
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.5V
V
CC
t
CDR
CE≧V
CC
- 0.2V
t
R
V
IH
CE
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
CC
V
DR
≧1.5V
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BS616LV2019
4
Revision 1.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
