BSI
BS616LV2021
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1269
1269
MAY CHANGE
FROM L TO H
WILL BE
3.3V
3.3V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
5PF
ANY CHANGE
PERMITTED
INCLUDING
INCLUDING
Ω
Ω
1404
1404
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC, Vcc =3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS616LV2021-70
MIN. TYP. MAX.
BS616LV2021-10
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
UNIT
tAVAX
tAVQV
tE1LQV
tE2LQV
tBA
tRC
Read Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
35
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
50
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS1
tACS2
Chip Select Access Time
(CE1)
(CE2)
--
--
Chip Select Access Time
--
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
(LB,UB)
--
--
tGLQV
tELQX
tBE
tOE
--
--
tCLZ
tBE
(CE1,CE2)
(LB,UB)
10
10
10
0
15
15
15
0
--
--
tGLQX
tEHQZ
tBDO
tOLZ
tCHZ
tBDO
tOHZ
tOH
--
--
(CE1,CE2)
(LB, UB)
35
35
30
--
40
40
35
--
0
0
tGHQZ
tAXOX
0
0
10
15
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
Revision 2.4
April 2002
R0201-BS616LV2021
6
BSI [ BRILLIANCE SEMICONDUCTOR ]
