ISG3300A1
PIN FUNCTIONS
Pin No.
Pin Name
Description
Equivalent Circuit
11
CLK
Clock pin for the dual P
LL
. High impedance
CMOS input. Data for the various latches is
clocked in on the rising edge into a 20-bit
shift register.
Serial data pin for the dual P
LL
. High
impedance CMOS input. MSB entered first.
The last two bits are the control bits.
Latch enable pin for the dual PLL. High
impedance CMOS input. When LE goes
HIGH, data stored in the shift registers is
loaded into one of the 4 latches determined
by the 2 control bits.
12
DATA
13
LD
EN
14
GND
Ground.
15
IF
OUT+
Non-inverting final IF output.
240 5.6
µH
15
16
IF
OUT-
Inverting final IF output.
240 5.6
µH
16
Note:
1. For programming information, refer to National LMX2336 data sheet (http://www.national.com)
FIGURE 1
91-860 MHz
43.75 MHz
RX OUT
DUAL PLL
CABLE
IN/OUT
CLK DATA LD
EN
OPTIONAL
TX IN
5-42 MHz
CEL [ CALIFORNIA EASTERN LABS ]
