ISG3300A1
VCO CHARACTERISTICS
Serial Data Input Timing
DATA
N20: WSB
(R20: WSB)
N19
(R19)
N10
(R10)
N9
(R9)
C2
(R8) (C2)
t
CWL
LE
OR
LE
t
CS
t
CH
t
CWH
t
ES
t
EW
C1: LSB
(C1: LSB)
(1)
VCO Output Frequency
CLOCK
(2)
VCO Input Voltage
Table 3. The F
O
LD Output Truth Table
RF1 R (19) RF2 R (19) RF1 R (20)
(RF1 LD) (RF2 LD)
(RF1 F
O
)
0
0
0
0
1
0
1
1
X
X
X
0
1
0
0
1
0
0
0
1
0
RF2 R (20)
F
O
LD
(RF2 F
O
) Output State
0
Disabled
1
0
RF2 Lock
Detect
2
0
RF1 Lock
Detect
2
0
RF1/RF2
Lock Detect
2
1
RF2 Reference
Divider Output
0
RF1 Reference
Divider Output
1
RF2
Programmable
Divider Output
0
RF1
Programmable
Divider Output
1
Fastlock
3
1
For internal
use only
1
For internal
use only
1
Counter Reset
4
Notes:
1. Parenthesis data indicates programmable reference
divider data.
2. Data shifted into register on clock rising edge.
3. Data is shifted in MSB first.
Test Conditions:
The Serial Data Input Timing is tested using a symmetrical
waveform around V
CC
/2. The test waveform has an edge
rate of 0.6V/ns with amplitudes of 2.2 V @ V
CC
= 2.7 V and
2.6 V @ V
CC
= 5.5 V.
Phase Comparator and Internal Charge Pump Character-
istics.
fr
fp
X
1
1
LD
0
0
1
1
0
1
0
1
1
1
1
1
Do
H
Z
f =f
r p
L
f <f
r p
f <f
r p
f <f
r p
f >f
r p
X - Don’t care condition
Notes:
1. When the F
O
LD output is disabled, it is actively pulled to a
low logic state.
2. Lock detect output provided to indicate when the VCO fre-
quency is in “lock”. When the loop is locked and a lock
detect mode is selected, the pin's output is HIGH, with nar-
row pulses LOW. In the RF1/RF2 lock detect mode a locked
condition is indicated when RF2 and RF1 are both locked.
3. The Fastlock mode utilized the F
O
LD output pin to switch a
second loop filter damping resistor to ground during fastlock
operation. Activation of Fastlock occurs whenever the RF
loop’s Icpo magnitude bit #17 is selected HIGH (while the
#19 and #20 mode bits are set for Fastlock).
4. The Counter Reset mode bits R19 and R20 when activated
reset all counters. Upon removal of the Reset bits the N
counter resumes counting in “close” alignment with R
counter. (The maximum error is one prescaler cycle). If
the Reset bits are activated the R counter is also forced to
Reset, allowing smooth acquisition upon powering up.
Notes:
1. Phase difference detection range: -2π to +2π
2. The minimum width pump up and pump down current pulses
occur at the D
O
pin when the loop is locked.
CALIFORNIA EASTERN LABORATORIES
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PRINTED IN USA -5/99
THIS PRODUCT HAS PATENT PENDING
DATA SUBJECT TO CHANGE WITHOUT NOTICE
CEL [ CALIFORNIA EASTERN LABS ]
