NEC'
S
7.5 V UHF BAND
NE5511279A
RF POWER SILICON LD-MOS FET
FEATURES
• HIGH OUTPUT POWER:
P
out
= 40.0 dBm TYP., f = 900 MHz, V
DS
= 7.5 V,
P
out
= 40.5 dBm TYP., f = 460 MHz, V
DS
= 7.5 V,
• HIGH POWER ADDED EFFICIENCY:
η
add
= 48% TYP., f = 900 MHz, V
DS
= 7.5 V,
5.7 MAX.
0.6±0.15
OUTLINE DIMENSIONS
(Units in mm)
PACKAGE OUTLINE 79A
(Bottom View)
4.2 MAX.
1.5±0.2
Source
Source
21001
4.4 MAX.
• HIGH LINEAR GAIN:
G
L
= 15.0 dB TYP., f = 900 MHz, V
DS
= 7.5 V,
G
L
= 18.5 dB TYP., f = 460 MHz, V
DS
= 7.5 V,
• SURFACE MOUNT PACKAGE:
5.7 x 5.7 x 1.1 mm MAX
W
0.4±0.15
5.7 MAX.
0.8±0.15
1.0 MAX.
0.8 MAX.
3.6±0.2
APPLICATIONS
• UHF RADIO SYSTEMS
• CELLULAR REPEATERS
• TWO-WAY RADIOS
• FRS/GMRS
• FIXED WIRELESS
DESCRIPTION
NEC's NE5511279A is an N-Channel silicon power laterally
diffused MOSFET specially designed as the transmission
power amplifier for 7.5 V radio systems. Die are manu-
factured using NEC's NEWMOS1 technology and housed in
a surface mount package. This device can deliver 40.0 dBm
output power with 48% power added efficiency at 900 MHz
using a 7.5 V supply voltage.
(T
A
= 25°C)
MIN
38.5
−
42
−
−
−
−
−
−
−
1.0
−
−
20
TYP
40.0
2.5
48
15.0
40.5
2.75
50
18.5
−
−
1.5
5
2.3
24
MAX
−
−
−
−
−
−
−
−
100
100
2.0
−
−
−
UNIT
dBm
A
%
dB
dBm
A
%
dB
nA
nA
V
°C/W
S
V
TEST CONDITIONS
f = 900 MHz, V
DS
= 7.5 V,
P
in
= 27 dBm,
I
DSQ
= 400 mA (RF OFF)
P
in
= 5 dBm
f = 460 MHz, V
DS
= 7.5 V,
P
in
= 25 dBm,
I
DSQ
= 400 mA (RF OFF)
P
in
= 5 dBm
V
GS
= 6.0 V
V
DS
= 8.5 V
V
DS
= 4.8 V, I
DS
= 1.5 mA
Channel to Case
V
DS
= 3.5 V, I
DS
= 900 mA
I
DSS
= 15
μA
ELECTRICAL CHARACTERISTICS
SYMBOL
P
out
I
D
η
add
G
L
P
out
I
D
η
add
G
L
I
GSS
I
DSS
V
th
R
th
g
m
BV
DSS
PARAMETER
Output Power
Drain Current
Power Added Efficiency
Linear Gain
Output Power
Drain Current
Power Added Efficiency
Linear Gain
Gate to Source Leak Current
Drain to Source Leakage Current
(Zero Gate Voltage Drain Current)
Gate Threshold Voltage
Thermal Resistance
Transconductance
Drain to Source Breakdown Voltage
Notes:
DC performance is 100% tested. RF performance is tested on several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
0.9±0.2
California Eastern Laboratories
0.2±0.1
• SINGLE SUPPLY:
V
DS
= 2.8 to 8.0 V
1.2 MAX.
η
add
= 50% TYP., f = 460 MHz, V
DS
= 7.5 V,
3
Gate
Drain
Gate
Drain
CEL [ CALIFORNIA EASTERN LABS ]
