EP7311
High-Performance, Low-Power System on Chip
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CI/O
Transceiver capacitance
8
-
10.0
pF
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 25 C
-
-
77
41
-
-
µA
µA
µA
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 70 C
-
-
-
-
570
111
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
IDDSTANDBY
@ 85 C
-
-
-
-
1693
163
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
VIL = GND 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD 0.1 V, VIL
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDidle
-
-
6
10
-
-
mA
V
at 74 MHz
= GND 0.1 V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
VDDSTANDBY
Standby supply voltage
2.0
-
-
a.
b.
c.
Refer to the strength column in the pin assignment tables for all package types.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note: 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
14
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(All Rights Reserved)
DS506F1
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