CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.4 Transmit Control Registers
0x60—DL_CTRL_STAT (HDLC Data Link Control and Status Register)
The DL_CTRL_STAT register is located at address 0x60. The eight LSBs of this register are control bits and
can be read or written. The eight MSBs are status bits and can only be read. Programming of the HDLC data
link is discussed in Section 2.8.
Field
Size
Bit
15
Name
Description
1
Receiver Interrupt
Indicates that the receiver needs service. A read to DL_CTRL_STAT clears this
interrupt.
14
1
3
1
1
1
1
1
3
1
Transmitter
Interrupt
Indicates that the transmitter needs service. A write to DL_CTRL_STAT clears this
interrupt.
13–11
RX Bytes[2:0]
Idle Code Received
Bad FCS
A 3-bit pointer to the last location written in the receive message buffer by the data
link receiver.
10
9
Indicates that an idle flag sequence (0111 1110) was received on the receive data
link.
Set when an erroneous Frame Check Sequence (FCS) was received at the end of a
message or an idle flag is received that is not byte aligned.
8
Abort Flag Received
Set if an abort sequence (seven consecutive 1s) was received on the receive data
link.
7
Enable Receive Data
Link Interrupt
Enables the receiver interrupt to appear on the DL_INT output pin.
6
Disable Data Link
Transmission
Forces the data link bits to all 1s.
5–3
2
TX Bytes[2:0]
A 3-bit pointer to the transmit message buffer indicating the location of the last byte
to be transmitted.
Abort Message
Causes the data link transmitter to halt the message in progress, send an abort flag,
and then resume transmission of idle flags on the data link.
1
0
1
1
Send FCS
Controls the transmission of the FCS at the end of a message block.
Send Message
Instructs the transmitter to begin transmission of a message block on the data link.
Setting this bit removes the data link from idle flag transmission mode and enables
transmitter interrupts to the controller for data bytes.
100046C
Conexant
3-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
