4.0 Electrical and Mechanical Specifications
CN8223
4.3 Timing
ATM Transmitter/Receiver with UTOPIA Interface
4.3.2 Line Interface Timing
Tables 4-3 through 4-6 and Figures 4-2 through 4-5 display the timing
requirements and characteristics of the line interfaces and parallel data and
overhead ports. All times are in nanoseconds. Example LIU circuits are provided
in CN8223 EVM schematics.
Table 4-3. Line Interface Timing—DS1, E1, DS3, E3 External Framers
Name
Interval
1–7
Description
Min
22
Max
—
Transmit Clock Period(1)
t
txcki
Transmit Clock Pulse Width High(2)
t
1–4
8.8
0
—
txh
t
t
3–4
Transmit Sync Setup to Transmit Clock Falling Edge
Transmit Sync Hold after Transmit Clock Falling Edge
—
tsck
ckts
4–6
2.4
2.9
2.9
22
—
t
t
t
1–2
Transmit Clock Rising Edge to DS1/E1 Serial Data Out
Transmit Clock Falling Edge to DS3/E3 Serial Data Out
Receive Clock Period
12.2
10.4
—
ckd1
ckd2
rxcki
4–5
8–13
8–11
9–11
11–12
10–11
11–14
Receive Clock Pulse Width High(2)
t
8.8
0
15
rxh
t
Receive Sync Setup to Receive Clock Falling Edge
—
rsck
ckrs
rdck
ckdr
t
Receive Sync Hold after Receive Clock Falling Edge
Receive Data Setup to Receive Clock Falling Edge
Receive Data Hold after Receive Clock Falling Edge
3.4
2.3
2.6
—
t
t
—
—
NOTE(S):
(1)
Nominal clock periods are:
DS1 –648 ns
E1 –488 ns
E3 –29.1 ns
DS3 –22.4 ns
(2)
Duty cycle must be 40/60 at maximum input clock rate.
4-6
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
