4.0 Electrical and Mechanical Specifications
CN8223
4.3 Timing
ATM Transmitter/Receiver with UTOPIA Interface
Figure 4-3. Line Interface Timing–Internal Framers
1
5
6
TXCKI,TXCKIHS
2
TCLKO
3
4
TXDATO
TXPOS, TXNEG
7
10
11
RXCKI,RXCKIHS
RXDATI
8
9
12
13
RXPOS, RXNEG
Table 4-5. Parallel Interface Timing
Name
Interval
1–4
Description
Min
50
Max
—
t
Transmit Clock Period
txcki
Transmit Clock Pulse Width High(1)
Transmit Clock In to Data Out
t
4–5
20
—
txh
t
1–2
4.6
3.9
0
16.5
14.6
—
cid
t
1–3
Transmit Clock In to Delineation Out
cdel
dscr
dhcf
rxcki
t
t
6–7
Transmit Disable Setup to Transmit Clock Rising Edge
Transmit Disable Hold after Transmit Clock Falling Edge
Receive Clock Period
8–9
3.0
50
—
t
11–15
11–13
10–11
11–14
12–13
15–16
—
Receive Clock Pulse Width High(1)
t
20
—
rxh
t
t
Receive Data Setup to Receive Clock Falling Edge
2.3
3.7
3.0
3.0
—
dck
ckd
Receive Data Hold After Receive Clock Falling Edge
Receive Disable Setup to Receive Clock Rising Edge
Receive Disable Hold after Receive Clock Falling Edge
—
t
—
dsck
ckds
t
—
NOTE(S):
(1)
Duty cycle must be 45/55 at maximum input clock rate.
4-8
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
