CN8223
4.0 Electrical and Mechanical Specifications
ATM Transmitter/Receiver with UTOPIA Interface
4.3 Timing
Figure 4-2. Line Interface Timing—DS1, E1, DS3, E3 External Framers
1
4
7
TXCKI,TXCKIHS
3
6
TXSYI
2
TXDATO (DS1/E1)
5
TXDATO (DS3/E3)
RXCKI,RXCKIHS
8
11
13
9
12
RXSYI
14
10
RXDATI
Table 4-4. Line Interface Timing—Internal Framers
Name
Interval
1–6
Description
Min
6.4
2.9
2.6
1.0
0.1
6.4
2.9
1.0
0.8
0
Max
—
Transmit Clock Period(1)
Transmit Clock Pulse Width High(2)
t
txcki
t
1–5
—
txh
t
1–2
Transmit Clock In to Clock Out Delay (non-inverted)
Transmit Clock Out to Transmit Data Out
Transmit Clock Out to Transmit Pos/Neg Out
Receive Clock Period
10.0
4.0
1.0
—
cico
t
2–3
cod
t
2–4
copn
t
7–11
7–10
8–10
10–12
9–10
10–13
rxcki
Receive Clock Pulse Width High(2)
t
—
rxh
t
Receive Data Setup to Receive Clock Falling Edge
—
rdck
ckrd
pnck
ckpn
t
Receive Data Hold after Receive Clock Falling Edge
Receive Pos/Neg Setup to Receive Clock Falling Edge
Receive Pos/Neg Hold after Receive Clock Falling Edge
—
t
t
—
3.5
—
NOTE(S): -
(1)
Nominal clock periods are: E3 –29.1 ns STS-3c – 6.4 ns
STS-1 –19.3 ns
E4 –7.2 ns
Duty cycle must be 45/55 at maximum input clock rate.
D3 – 22.4 ns
(2)
100046C
Conexant
4-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
