Bt8370/8375/8376
3.16 Data Link Registers
Fully Integrated T1/E1 Framer and Line Interface
RMPTY1
Receive FIFO Empty—Indicates no data or status bytes are present in the receive data link
FIFO.
0 = FIFO contains data or status as indicated by RSTAT1
1 = FIFO empty
RNEAR1
Receive FIFO Near Full—Indicates the data link has filled the receive FIFO to the near full
threshold level specified in FFC[5:0]. Upon reaching that level, the receiver updates the
message status byte [WORD0] placed on top of the FIFO and reports the current in-progress
message with a Partial end of message status. The processor must read those filled FIFO
locations to clear the RNEAR1 status indicator and enable the next RNEAR interrupt.
0 = FIFO depth is below the near full level
1 = FIFO is filled to the near full level
RFULL1
Receive FIFO Full—Indicates the data link has completely filled 64 byte locations in the
receive FIFO. In all cases, RFULL1 is an error indicating that the processor did not keep pace
with the receiver and that one or more received messages were discarded after the FIFO
became full. The FIFO can still contain one or more Good received messages, and the
processor can still process all receive FIFO contents as usual. However, any message in
progress when FIFO reached full is discarded and reported with a Partial end of message status
and a 0 byte count (which distinguishes a full end of message status from a normal abort or
error message status).
0 = FIFO is less than full
1 = FIFO has been completely filled
0AA—Performance Report Message (PRM)
7
6
5
4
3
2
1
0
AUTO_PRM
PRM_CR
PRM_R
PRM_U1
PRM_U2
PRM_SL
AUTO_SL
SEND_PRM
AUTO_PRM
Automatic PRM Insertion—AUTO_PRM instructs the data link transmitter to format and send
a Performance Report Message on the selected transmit channel after each occurrence of the
ONESEC interrupt. To meet PRM requirements specified in ANSI T1.403-1995, both FCS
mode [DL1_CTL; addr 0A6] and 1-second error count latching [LATCH_CNT; addr 046]
must be enabled, and the data link channel must be selected to output on Facility Data Link
(FDL) framing bits [DL1_TS=0x40; addr 0A4]. Octets 1–14 of the transmit PRM message
contents are automatically encoded (as shown in Figure A-5, Performance Report Message
Structure), based on the number of received CRC, FPS, LCV, SEF, and FRED errors
[addr 050-05A]. RFSLIP errors [SSTAT; addr 0D9] are also automatically encoded if
AUTO_SL (described below) is enabled. The remaining PRM message contents typically
remain fixed and are supplied by the processor from other bits that follow in the PRM register.
BOP priority codeword transmissions are interrupted by AUTO_PRM, if TDL1 is granted
output priority [TBOP_MODE=11; addr 0A0].
AUTO_PRM messages take up no space in the transmit data link FIFO, but are inserted on
the transmit channel only after the FIFO is empty. Therefore, if the processor needs to transmit
another type of FDL message between PRM messages, the processor must write that message
after AUTO_PRM has begun sending (i.e., after ONESEC interrupt).
0 = no automatic PRM
1 = send PRM automatically every ONESEC
3-98
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
