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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
Fully Integrated T1/E1 Framer and Line Interface  
3.16 Data Link Registers  
TNEAR1  
Transmit FIFO Near EmptyIndicates that the data link has emptied the transmit FIFO to  
below the near empty threshold specified in FEC[5:0]. After sending the byte that occupied the  
near empty FIFO threshold level, TNEAR1 goes active-high, which generates a TNEAR  
interrupt. The processor must write data to TDL1 to fill the transmit FIFO beyond the near  
empty threshold. This is necessary to clear TNEAR1 status, and enable the next TNEAR  
interrupt event.  
0 = FIFO depth is below the near empty level  
1 = FIFO has been emptied past the near empty level  
TFULL1  
Transmit FIFO FullIndicates that the processor has completely filled 64 byte locations in  
transmit FIFO. While TFULL1 remains active, any subsequent processor-writes to TDL1 are  
ignored. If the processor inadvertently writes to TDL1 while TFULL1 is active, the processor  
must allow FIFO to become completely empty without writing to TDL1_EOM. This is  
necessary to force the transmitter to send an abort character.  
0 = FIFO is less than full  
1 = FIFO has been completely filled  
0AFDL2 Time Slot Enable (DL2_TS)  
NOTE:  
Not available in Bt8376 device.  
7
6
5
4
3
2
1
0
DL2_TS[7]  
DL2_TS[6]  
DL2_TS[5]  
DL2_TS[4]  
DL2_TS[3]  
DL2_TS[2]  
DL2_TS[1]  
DL2_TS[0]  
DL2_TS[7]  
DL2_TS[6, 5]  
UnchannelizedTest mode only, all time slots selected. Zero for normal operation.  
Frame SelectTransmit and receive data link 2 operates on data only during specified T1/E1  
frames. Frame select options give the processor access to different types of data link channels  
and overhead channels. Overhead bit insertion is performed after TDL1, so internal transmitter  
overhead insertion must be bypassed [TFRM; addr 072] before the processor-supplied  
overhead can be output from TDL2.  
00 = all frames  
01 = even frames only  
10 = odd frames only  
11 = reserved  
DL2_TS[4:0]  
Time Slot Word EnableTransmit and receive data link 2 operates on data only during the  
specified time slot. During T1 mode, selecting time slot 0 enables data link operation on the  
F-bit positions.0B0DL2 Bit Enable (DL2_BIT)  
DL2_TS[4:0]  
00000  
00001  
|
Time Slot Enable  
F-bit (T1) or TS0 (E1)  
TS1  
|
11110  
11111  
TS30  
TS31  
N8370DSE  
Conexant  
3-101