Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.7 Receive LIU Registers
020—LIU Configuration (LIU_CR)
NOTE:
Bits 0 and 1 are reserved and should be written to the values shown.
7
6
5
4
3
2
1
0
RST_LIU
SQUELCH
FORCE_VGA
RDIGI
ATTN[1]
ATTN[0]
0
1
RST_LIU
Reset RLIU—Writing a 1 to RST_LIU resets the RLIU, reinitializes the receive equalizer, and
re-attempts signal acquisition. The processor must reset the RLIU after changing ATTN, or
after changing equalizer coefficients [EQ_DAT; addr 025]. Optionally, it can be reset in
response to an extended alarm condition.
0 = normal
1 = reset RLIU (self clears)
SQUELCH
Enable Squelch—Data slicer outputs from RLIU are forced to 0 until EYEOPEN [addr 021] =
1. SQUELCH is useful for long haul applications when near-end crosstalk may be of sufficient
magnitude to prevent accurate loss of signal detection.
0 = no effect
1 = squelch data slicer output
FORCE_VGA
RDIGI
FORCE VGA—Internal Variable Gain Amplifier (VGA) is set to equal the value programmed
in VGA_MAX register (addr 024). This bit is used for test purposes only.
0 = normal operation
1 = force VGA to VGA_MAX (test mode only)
Enable Receive Digital Inputs—When set, RDIGI bypasses RLIU and enables
RPOSI/RNEGI/RCKI inputs provided by an external line interface; otherwise, bipolar
RTIP/RRING inputs are enabled, RCKI input is ignored, and RPLL recovers the received
clock.
0 = RTIP/RRING inputs enabled
1 = RPOSI/RNEGI/RCKI inputs enabled
ATTN[1:0]
Bridge Attenuation—The receive equalizer can automatically compensate for signal level
attenuation caused by placement of bridge resistors in series with the normal receive
termination resistance. Bridge compensation scales the equalizer coefficients because they are
loaded from internal ROM; therefore, any change to the ATTN setting must be followed by an
RLIU reset command (RST_LIU).
ATTN
00
Bridge Attenuation
0 dB
Bridge Resistance
None
01
–10 dB
300 Ω
10
–20 dB
1000 Ω
11
–30 dB
1500 Ω
N8370DSE
Conexant
3-39
CONEXANT [ CONEXANT SYSTEMS, INC ]
