Bt860/861
5.0 Serial Programming Interface and Registers
5.1 Serial Interface
Multiport YCrCb to NTSC/PAL /SECAM
Figure 5-2. Serial Programming Interface Typical Write Sequence
Chip Write
Address
88 or 8A
S
A
Sub Address
A
Data
A
Data
A
P
Optional Sequential
Write May be Repeated
S = Start Condition
P = Stop Condition
A = Acknowledge
From Master
From Bt860/861
861_036
5.1.3 Reading Data
A read transaction involves sending the device address byte with the read/write*
bit high, and receiving one or more bytes after changing the direction of the bus.
The first byte returned after the device address byte is the contents of the last
indexed register subaddress. Any subsequent data bytes read come from registers
whose address follows in ascending order as the internal subaddress pointer is
incremented at the completion of every read. The initial register subaddress
depends on the state of the pointer at the end of the last write transaction. Because
writing even one data byte to a register will increment the subaddress pointer,
typically one would want to precede a read with a write transaction that sends
only the register subaddress byte.
Figure 5-3 illustrates a typical register read sequence.
1. Master transmits the device address with the read/write* bit low.
2. Master transmits the desired register subaddress.
3. Master generates repeat start.
4. Master transmits the device address with the read/write* bit high.
5. Slave (Bt860/861) transmits the data byte to master.
6. Subsequent registers are read until a stop condition is detected.
Figure 5-3. Serial Programming Interface Typical Read Sequence
Chip Write
Address
Chip Read
Address
S
A
Sub Address
A
Sr
A
Data
A
Data
NA P
88 or 8A
89 or 8B
Optional Sequential
Read May be Repeated
S = Start Condition
P = Stop Condition
From Master
From Bt860/861
A = Acknowledge
Sr = Repeat Start Condition
NA = Not Acknowledged
861_037
D860DSA
Conexant
5-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
