Bt860/861
4.0 Applications
Multiport YCrCb to NTSC/PAL /SECAM
4.1 PC Board Considerations
4.1.8 Digital Signal Interconnect
The digital inputs to the Bt860/861 should be isolated from the analog outputs
and other analog circuitry as much as possible and should not overlay the analog
power plane.
Most noise on the analog outputs is caused by excessive edge rates (less than
3 ns), overshoot, undershoot, and ringing on the digital inputs coupling into the
analog signals. Ringing can be reduced by damping the line with a series resistor
(30–300 Ω).
Because feed-through noise is proportional to the digital edge rates,
lower-speed logic (3–5 ns edge rates) should be used whenever possible. Route
the digital signals at 90-degree angles to any analog signals.
4.1.9 Analog Signal Interconnect
Locate the Bt860/861 as close as possible to the output connectors to minimize
noise pickup and reflections caused by impedance mismatch. The video output
signals should overlay the ground plane.
The analog outputs are susceptible to crosstalk from digital lines; digital traces
must not be routed under or adjacent to the analog output traces.
For maximum performance, the analog video output impedance, cable
impedance, and load impedance should be identical. The load resistor connection
between the video outputs and AGND should be as close as possible to the
Bt860/861 to minimize reflections. Turn off all unused analog outputs by setting
the applicable EN_DAC_x register bit to 0.
4.1.10 ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device
damage, which can produce symptoms ranging from catastrophic failure to erratic
device behavior with leaky inputs.
All logic inputs should be held low until power to the device has settled to the
specified tolerance. DAC power decoupling networks with large time constants
should be avoided; they could delay VAA and VDD power to the device. Ferrite
beads must be used only for analog power VAA decoupling. Inductors cause a
time constant delay that induces latchup, and should not be substituted for ferrite
beads.
Latchup can be prevented by ensuring that all power pins are at the same
potential, all GND pins are at the same potential, and that the VAA and VDD
supply voltages are applied before the signal pin voltages. The correct power-up
sequence ensures that any signal pin voltage will never exceed the power supply
voltage.
D860DSA
Conexant
4-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
